SC68C752BIBS,157 NXP Semiconductors, SC68C752BIBS,157 Datasheet - Page 30

• Manufacturer Part Number: SC68C752BIBS,157
• Description: IC UART DUAL 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIBS,157

• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280969157; SC68C752BIBS; SC68C752BIBS

NXP Semiconductors
SC68C752B_4
Product data sheet
7.13 Trigger Level Register (TLR)
7.14 FIFO ready register
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before auto-RTS or software flow control is enabled to avoid spurious operation
of the device.
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4.
Table 22.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logic 0, the selectable trigger levels via the FIFO control register (FCR) are
used for the transmit and receive FIFO trigger levels. Trigger levels from
4 bytes to 60 bytes are available with a granularity of four. The TLR should be
programmed for
When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting
defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is
discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
that is, ‘00’.
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
Table 23.
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CS = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is
disabled. The address is 111.
Bit
7:4
3:0
Bit
7:6
5
4
3:2
1
0
Symbol
TLR[7:4]
TLR[3:0]
Symbol
FIFO Rdy[7:6]
FIFO Rdy[5]
FIFO Rdy[4]
FIFO Rdy[3:2]
FIFO Rdy[1]
FIFO Rdy[0]
Trigger Level Register bits description
FIFO ready register bits description
Table 22
N
Description
receive FIFO trigger levels (4 to 60), number of characters available.
transmit FIFO trigger levels (4 to 60), number of spaces available.
⁄
4
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
, where N is the desired trigger level.
Rev. 04 — 20 January 2010
shows trigger level register bit settings.
Description
unused; always 0
receive FIFO B status; related to DMA
receive FIFO A status; related to DMA
unused; always 0
transmit FIFO B status; related to DMA
transmit FIFO A status; related to DMA
SC68C752B
© NXP B.V. 2010. All rights reserved.
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