SC68C752BIBS,157 NXP Semiconductors, SC68C752BIBS,157 Datasheet - Page 13

• Manufacturer Part Number: SC68C752BIBS,157
• Description: IC UART DUAL 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIBS,157

• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280969157; SC68C752BIBS; SC68C752BIBS

NXP Semiconductors
SC68C752B_4
Product data sheet
6.5 Interrupts
The SC68C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of
interrupts and the IRQ signal in response to an interrupt generation. The IER can also
disable the interrupt system by clearing bits 3:0 and bits 7:5. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of interrupt
through IIR[5:0].
Table 7.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
IIR[5:0]
000001
000110
001100
000100
000010
000000
010000
100000
Priority
level
None
1
2
2
3
4
5
6
Interrupt control functions
Table 7
Interrupt type
none
receiver line
status
RX time-out
RHR interrupt
THR interrupt
Xoff interrupt
CTS, RTS
modem status
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
summarizes the interrupt control functions.
none
stale data in RX FIFO
DRDY (data ready)
RTSn pin or CTSn pin change
Interrupt source
OE, FE, PE, or BI errors occur
in characters in the RX FIFO
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger
level
(FIFO enable)
MSR[3:0] = 0
receive Xoff character(s)/
special character
state from active (LOW) to
inactive (HIGH)
read RHR
read MSR
Interrupt reset method
none
FE, PE, BI: all erroneous
characters are read from
the RX FIFO.
OE: read LSR
read RHR
read IIR or a write to the
THR
receive Xon character(s)/
Read of IIR
read IIR
SC68C752B
© NXP B.V. 2010. All rights reserved.
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