sc68c752b NXP Semiconductors, sc68c752b Datasheet
sc68c752b
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sc68c752b Summary of contents
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... The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates Mbit/s. The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software fl ...
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... Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1: Type number SC68C752BIB48 LQFP48 SC68C752BIBS SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Ordering information ...
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... R/W CONTROL RESET REGISTER SELECT CS IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC68C752B SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs AND LOGIC LOGIC CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 03 — 29 November 2005 ...
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... TXB 8 OPB n.c. 12 terminal 1 index area RXB RXA 4 SC68C752BIBS TXA 5 TXB 6 7 OPB CS 8 Transparent top view Rev. 03 — 29 November 2005 SC68C752B 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OPA 31 RXRDYA 30 IRQ 29 n. n.c. 002aab018 24 RESET 23 RTSA 22 OPA ...
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... Data Terminal Ready (active LOW). These outputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates that the SC68C752B is powered-on and ready. These pins can be controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem. ...
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... A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an external CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH on this pin will load the contents of an internal register defined by address bits A[0:2] on the SC68C752B data bus (D[0:7]) for access by an external CPU. - ...
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... Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output. Channel selection using CS pin A3 UART channel - none 0 Channel A 1 Channel B Rev. 03 — 29 November 2005 SC68C752B Figure 13). Alternatively, © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... The complete status of each channel of the SC68C752B UART can be read at any time during functional operation by the processor. The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels ...
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... Fig 4. Auto flow control (Auto-RTS and Auto-CTS) example 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see SC68C752B” on page levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted ...
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... Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Rev. 03 — 29 November 2005 SC68C752B Start byte Stop 002aaa227 shows software flow control options. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 Receive flow control When software flow control operation is enabled, the SC68C752B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character ...
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... SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD compare Xoff2 WORD programmed Xon-Xoff characters st Rev. 03 — 29 November 2005 SC68C752B UART2 RECEIVE FIFO SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon2 WORD Xoff1 WORD Xoff2 WORD 002aaa229 character while UART2 is sending the Xoff © ...
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... Reset control RESET RESET RESET RESET RESET Rev. 03 — 29 November 2005 SC68C752B Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (1Dh) all bits cleared bits 5 and 6 set; all other bits cleared bits cleared ...
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... Philips Semiconductors 6.5 Interrupts The SC68C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the IRQ signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0:3, 5:7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... Fig 9. FIFO Polled mode operation SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Figure 8 shows Interrupt mode operation. R/W IRQ PROCESSOR R/W PROCESSOR Rev. 03 — 29 November 2005 SC68C752B IIR IER THR RHR 002aab096 Figure 9 shows FIFO ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs shows TXRDY and RXRDY in DMA mode 0/FIFO disable. TX TXRDY at least one location filled TXRDY FIFO EMPTY Rev. 03 — 29 November 2005 SC68C752B RX RXRDY at least one rdptr location filled RXRDY FIFO EMPTY rdptr 002aaa232 © ...
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... It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC68C752B UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • ...
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... When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC68C752B UART contains a programmable baud generator that takes any clock input and divides divisor in the range between 1 and (2 divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 12 ...
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... Rev. 03 — 29 November 2005 SC68C752B Percent error difference between desired and actual 0.026 0.058 0.69 2.86 Percent error difference between desired and actual 0.026 0.034 0.312 0.628 1.23 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Xoff1 word [2] [4] 1 Xoff2 word 0 Transmission Control Register (TCR) 1 Trigger Level Register (TLR) [2] [6] 1 FIFO ready register Rev. 03 — 29 November 2005 SC68C752B XTAL1 XTAL2 1 1.8432 MHz 002aaa870 Write mode Transmit Holding Register (THR) Interrupt Enable Register ...
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... This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled. [3] The Special register set is accessible only when LCR[7] is set to a logic 1. SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs lists and describes the SC68C752B internal registers. Bit 6 Bit 5 Bit 4 bit 6 bit 5 ...
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... If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 10 for more register access information. Rev. 03 — 29 November 2005 SC68C752B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... FIFO. FCR[0] FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO Rev. 03 — 29 November 2005 SC68C752B Table 12 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received bits bits bits bits Rev. 03 — 29 November 2005 SC68C752B Table 13 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LSR[0] Data in receiver. logic data in receive FIFO (normal default condition) logic least one character in the RX FIFO Rev. 03 — 29 November 2005 SC68C752B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... MSR[4]. If Auto-RTS is enabled, the RTS output is controlled by hardware flow control. MCR[0] DTR logic 0 = force DTR output to inactive (HIGH) logic 1 = force DTR output to active (LOW). In Loopback mode, controls MSR[5]. Rev. 03 — 29 November 2005 SC68C752B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... DSR. Indicates that DSR input (or MCR[0] in Loopback mode) has changed state. Cleared on a read. MSR[0] CTS. Indicates that CTS input (or MCR[1] in Loopback mode) has changed state. Cleared on a read. Rev. 03 — 29 November 2005 SC68C752B Table 16 shows Modem Status Register bit settings © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... THR interrupt Receive Holding Register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt Rev. 03 — 29 November 2005 SC68C752B Table 17 Section 6.7 “Sleep mode” for details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Rev. 03 — 29 November 2005 SC68C752B Table 19. 19. IIR[1] IIR[0] Source of the interrupt 1 0 receiver line status error 0 0 receiver time-out interrupt 0 0 RHR interrupt 1 0 THR interrupt 0 0 modem interrupt 0 ...
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... Transmission Control Register bits description Description RX FIFO trigger level to resume transmission (0 bytes to 60 bytes). RX FIFO trigger level to halt transmission (0 bytes to 60 bytes). Rev. 03 — 29 November 2005 SC68C752B Table 20 shows transmission control register bit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. shows 10 ...
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... The TLR should be programmed for When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger level setting. ...
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... Set flow control threshold to VALUE SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide Rev. 03 — 29 November 2005 SC68C752B Actions read LCR (03h), save in temp set LCR (03h) to 80h set DLL (00h) to VALUE1 set DLM (01h) to VALUE2 ...
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... Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide …continued Rev. 03 — 29 November 2005 SC68C752B Actions read LCR (03h), save in temp1 set LCR (03h) to BFh read EFR (02h), save in temp2 set EFR (02h) to 10h + temp2 ...
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... Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Limiting values Parameter Conditions supply voltage input voltage output voltage ambient temperature operating in free-air storage temperature Table 25 “Limiting values” Rev. 03 — 29 November 2005 SC68C752B [1] Min Max Unit - ...
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... V on non-hysteresis inputs. IH(max) Rev. 03 — 29 November 2005 SC68C752B V = 3.3 V and Min Typ Max + ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs = 10 %, unless specified otherwise. CC Conditions 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 8T [2] [3] Rev. 03 — 29 November 2005 SC68C752B 3.3 V and Min Max Min ...
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... Rev. 03 — 29 November 2005 SC68C752B valid address valid data 002aab087 valid address t d6 valid data 002aab088 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Figure 15. Figure 14 Rev. 03 — 29 November 2005 SC68C752B change of state t d8 active active t d9 active active t d8 change of state 002aab089 002aac020 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... data bits 6 data bits 7 data bits 16 baud rate clock Start bit data bits ( Rev. 03 — 29 November 2005 SC68C752B next data parity Stop Start bit bit bit d10 active t d11 active 002aab090 ...
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... Start bit data bits ( data bits 6 data bits 7 data bits t d12 t d13 16 baud rate clock Rev. 03 — 29 November 2005 SC68C752B parity Stop bit bit first byte that reaches the trigger level t d15 active data ready t d16 ...
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... data bits 6 data bits 7 data bits t d18 t d17 trigger lead Rev. 03 — 29 November 2005 SC68C752B next data parity Stop Start bit bit bit d18 transmitter not ready parity stop bit ...
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... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 29 November 2005 SC68C752B detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT313 ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 03 — 29 November 2005 SC68C752B detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT617 ISSUE DATE ...
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... SC68C752B_3 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 2 Rev. 03 — 29 November 2005 SC68C752B 3 350 mm so called so called small/thin packages. © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 03 — 29 November 2005 SC68C752B Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Abbreviations Description Central Processing Unit Direct Memory Access First In/First Out Least Significant Bit Most Significant Bit Universal Asynchronous Receiver and Transmitter Rev. 03 — 29 November 2005 SC68C752B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Xoff1, Xoff2, Xon1, Xon2 register names to XOFF1, XOFF2, XON1, XON2, respectively (Xoff1, Xoff2, Xon1, Xon2 character and word names remain as-is) • Table 10 “Register map - read/write • Table 11 “SC68C752B internal descriptions modified (removed “0/” and “0/X”) • Table 24 “Register programming guide” • ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 03 — 29 November 2005 SC68C752B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands SC68C752B Date of release: 29 November 2005 Document number: SC68C752B_3 ...