SC68C752BIBS,157 NXP Semiconductors, SC68C752BIBS,157 Datasheet - Page 15

IC UART DUAL 32HVQFN

SC68C752BIBS,157

Manufacturer Part Number
SC68C752BIBS,157
Description
IC UART DUAL 32HVQFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC68C752BIBS,157

Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280969157
SC68C752BIBS
SC68C752BIBS
NXP Semiconductors
SC68C752B_4
Product data sheet
6.6.1.1 Transmitter
6.6.1.2 Receiver
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)
6.6 DMA operation
There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by
FCR[3].
In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In
DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the
processor for longer periods of time.
Figure 10
When empty, the TXRDYn signal becomes active. TXRDYn will go inactive after one
character has been loaded into it.
RXRDYn is active when there is at least one character in the FIFO. It becomes inactive
when the receiver is empty.
Fig 10. TXRDYn and RXRDYn in DMA mode 0/FIFO disable
wrptr
wrptr
shows TXRDYn and RXRDYn in DMA mode 0/FIFO disable.
FIFO EMPTY
transmit
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
TXRDYn
TXRDYn
location filled
at least one
rdptr
rdptr
FIFO EMPTY
receive
SC68C752B
© NXP B.V. 2010. All rights reserved.
location filled
RXRDYn
RXRDYn
at least one
002aaa232
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