STEVAL-PCC010V2 STMicroelectronics, STEVAL-PCC010V2 Datasheet - Page 20

• Manufacturer Part Number: STEVAL-PCC010V2
• Description: BOARD EVAL FOR ST802RT1A
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-PCC010V2

• Design Resources: STEVAL-PCC010V2 BOM STEVAL-PCC010V2 Schematic
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: ST802RT1A, STM32F207
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11465

Description
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Nested vectored interrupt controller (NVIC)
The STM32F205xx and STM32F207xx embed a nested vectored interrupt controller able to
handle up to 87 maskable interrupt channels (not including the 16 interrupt lines of the
Cortex™-M3) and 16 priority levels.
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This hardware block provides flexible interrupt management features with minimum interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however, the 16 MHz internal RC oscillator
is selected as the default CPU clock on reset. An external 4-26 MHz clock can be selected,
in which case it is monitored for failure. If failure is detected, the system automatically
switches back to the internal RC oscillator. A software interrupt is generated if enabled.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the
system clock.
Several prescalers and PLLs allow the configuration of the two AHB buses, the high-speed
APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two
AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is
60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz.
In order to achieve audio class performance, a specific crystal can be used. In this case, the
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S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
Doc ID 15818 Rev 6
STM32F205xx, STM32F207xx