CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 9

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
CY7C1382C:Pin Definitions
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
0
Name
, A
1
2
3
A,
[2]
[2]
1
BW
, A
B
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
TQFP
93,94
88
87
89
98
97
92
86
83
C2,R2,
P4,N4,
A2,B2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
G3,L5
BGA
M4
H4
K4
E4
G4
F4
-
-
B2,B10,P3,P4,
R3,R4,R8,R9,
R6,P6,A2,
N6,P8,P9,
A10,A11,
P10,P11,
B5,A4
fBGA
R10,
R11
B7
A7
B6
A3
B3
A6
B8
A9
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
I/O
Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
CE
to the two-bit counter. .
Byte Write Select Inputs, active LOW. Qualified
with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK .
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE
ignored if CE
Chip Enable 2 Input, active HIGH. Sampled on
the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE
for AJ package version. Not connected for BGA.
Where referenced, CE
throughout this document for BGA.
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
2
1
, and CE
and CE
2
3
to select/deselect the device. Not available
to select/deselect the device. ADSP is
3
3
1
to select/deselect the device.
are sampled active. A1: A0 are fed
is HIGH.
Description
3
is assumed active
CY7C1380C
CY7C1382C
X
and BWE).
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