CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 11

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
CY7C1382C:Pin Definitions
V
MODE
TDO
TDI
TMS
TCK
NC
DDQ
Name
4,11,20,27,54,
1,2,3,6,7,
14,16,25,
28,29,30,
51,52,53,
56,57,66,
75,78,79,
61,70,
38,39,
TQFP
95,96
77
31
-
-
-
-
J1,J7,M1,M7,
N2,L7,P1,P6,
A1,A7,F1,F7,
K6,L4,L2,L7,
J3,J5,K1,
T1,T4,U6
C1,C7,
D2,D4,
G6,H7,
R5,R7,
B1,B7,
D7,E1,
E6,H2,
F2,G1,
U1,U7
BGA
M6,
R1,
R3
U5
U3
U2
U4
(continued)
C1,C2,C10,D1
G10,H1,H3,H9
K11,L2,L1,M2,
N2,N10,N5,N7
C3,C9,D3,D9,
L9,M3,M9,N3,
,H10,J2,J11,
E1,E10,F1,
N11,P1,A1,
F3,F9,G3,
A5,B1,B4,
G9,J3,J9,
K3,K9,L3,
F10,G1,
E3,E9,
P2,R2
fBGA
,D10,
M11,
B11,
K2,
N9
R1
R5
R7
P7
P5
I/O Power Sup-
Synchronous
Synchronous
Synchronous
JTAG-Clock
JTAG serial
JTAG serial
JTAG serial
output
Input-
Static
input
input
I/O
ply
-
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be left floating or connected to
V
able on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to V
Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to V
packages.
No Connects. Not internally connected to the die.
DD
DD
through a pull up resistor. This pin is not avail-
. This pin is not available on TQFP packages.
SS
. This pin is not available on TQFP
Description
CY7C1380C
CY7C1382C
Page 11 of 36
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