CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 14

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
Truth Table
Truth Table for Read/Write
Truth Table for Read/Write
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
WRITE Cycle,Suspend Burst
Notes:
Read
Read
Write Byte A – ( DQ
Write Byte B – ( DQ
Write Bytes B, A
Write Byte C – ( DQ
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQ
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Read
Read
Write Byte A – ( DQ
Write Byte B – ( DQ
Write Bytes B, A
Write All Bytes
Write All Bytes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) .
1
, CE
2
Operation
, and CE
Function (CY7C1380C)
[ 3, 4, 5, 6, 7, 8]
3
Function (CY7C1382C)
are available only in the TQFP package. BGA package has only 2 chip selects CE
B
C
D
B
A
A
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
B
D
C
B
A
A
Add. Used
)
)
)
)
)
)
[5]
[5]
Current
Current
Current
Current
Current
Current
Next
Next
Next
CE
H
H
H
H
X
H
X
X
X
1
GW
CE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
2
CE
X
X
X
X
X
X
X
X
X
3
BWE
ZZ ADSP
GW
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
X
H
X
H
H
X
X
H
X
BW
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
ADSC
D
BWE
1
H
H
H
H
H
H
H
H
H
and CE
H
X
L
L
L
L
L
X
. Writes may occur only on subsequent clocks
ADV WRITE OE CLK
2
.
H
H
H
H
H
H
L
L
L
BW
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
C
BW
H
H
H
H
H
L
L
L
L
X
H
H
X
L
L
L
B
BW
CY7C1380C
CY7C1382C
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
H
H
H
X
X
X
X
L
L
B
L-H Tri-State
L-H
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
Page 14 of 36
BW
H
H
X
L
L
L
X
BW
A
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
DQ
Q
Q
D
D
D
D
A
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