CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 7

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
CY7C1380C–Pin Definitions
Name
ADSP
ADSC
ZZ
DQs, DQPs
V
V
DD
SS
12,13,18,19,22
79,2,3,6,7,8,9,
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
23,24,25,
28,29,51,
15,41,65,
17,40,67,
80,1,30
TQFP
84
85
64
91
90
,
J2,C4,J4,R4,
M6,N6,
G6,H6,
G7,H7,
G1,H1,
G2,H2,
M2,N2,
K3,M3,
K5,M5,
N7,P7,
D7,E7,
D1,E1,
N1,P1,
P6,D6,
D3,E3,
N3,P3,
D5,E5,
K6,L6,
K7,L7,
E6,F6,
E2,F2,
K1,L1,
K2,L2,
F3,H3,
F5,H5,
D2,P2
N5,P5
BGA
(continued)
A4
B4
T7
J6
M5,M6,M7,N4,
G4,G8,H4,H8,
G7,H2,H5,H6,
G1,D2,E2,F2,
D4,D8,E4,E8,
C4,C5,C6,C7,
C8,D5,D6,D7,
F6,F7,G5,G6,
E5,E6,E7,F5,
H7,J5,J6,J7,
C11,C1,N1
K1,L1,M1,
D1,E1,F1,
K4,K8,L4,
L8,M4,M8
K5,K6,K7,
J2,K2,L2,
L10,M10,
D10,E10,
F10,G10,
L5,L6,L7,
M11,L11,
J10,K10,
D11,E11,
F11,G11,
K11,J11,
M2,N11,
G2,J1,
F4,F8,
J4,J8,
fBGA
H11
B9
A8
N8
Asynchronous
Power Supply Power supply inputs to the core of the de-
Synchronous
Synchronous
Synchronous
Ground
Input-
Input-
Input-
I/O-
I/O
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE
Address Strobe from Controller, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQP
placed in a tri-state condition.
vice.
Ground for the core of the device.
1
is deasserted HIGH.
Description
CY7C1380C
CY7C1382C
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