CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 28

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
Switching Waveforms
Read Cycle Timing
Notes:
21. On this diagram, when CE is LOW: CE
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
GW, BWE,
ADDRESS
ADSP
ADSC
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
[21]
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
is LOW, CE
t ADS
A2
Q(A1)
t ADH
t OEHZ
2
t ADVS
is HIGH and CE
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
t DOH
3
t CO
is LOW. When CE is HIGH: CE
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
X
LOW.
Q(A2 + 2)
BURST READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
CY7C1380C
CY7C1382C
3
Q(A2 + 1)
is HIGH.
t CHZ
Deselect
cycle
Page 28 of 36
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