CY7C1380C-167AI Cypress Semiconductor Corp, CY7C1380C-167AI Datasheet - Page 12

• Manufacturer Part Number: CY7C1380C-167AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380C-167AI

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05237 Rev. *D
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(200-MHz device).
The CY7C1380C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
1
1
, CE
is HIGH. The address presented to the address inputs (A)
1
, CE
2
, CE
2
, CE
3
are all asserted active, and (3) the Write
3
are all asserted active. The address
X
) inputs. A Global Write
1
, CE
2
, CE
CO
) is 3.0ns
3
) and an
1
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
signals. The CY7C1380C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1380C provides a two-bit wraparound counter, fed
by A1: A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
X
) are asserted active to conduct a Write to the desired
X
) input, will selectively write to only the desired
1
, CE
2
, CE
3
are all asserted active, and
CY7C1380C
CY7C1382C
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X
) and
X
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