CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 7

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
CPU Interface
POSIC2GVC can interface with 16-bit or 32-bit CPU. The CPU
interface can be pin configured to be compatible with Motorola
or Intel bus interface. The CPU interface provides access to
all registers of POSIC2GVC, collates all interrupt generated by
various blocks and also supports control packet transfers.
Line Interface
The line interface/fiber side interface is configurable as 8 bit,
16-bit or 32-bit depending on the clock frequency and data
rate. The options shown in Table 2 are available.
System Memory at
Host System
TTL-expired and
(CRC and Parity)
belonging to this
Errored packets
Node-sourced
packets to be
other discard
Control Packets
Packets not
packets
sinked
Node
Packets
........
Data
Tag #1
Tag #13
Tag #14
Tag #15
Data
Data
Data
Data
Data
Tag #2
Tag #0
Tag #n
Data
Figure 4. Frame Tagging Engine Data Sorting Diagram
Tagging enables sorting of packets by
CONFIDENTIAL
Table 2. Configuration Options
Clock Source
The transmit clock can be programmed to be one of the
following sources:
8 bits
8 bits
16 bits
16 bits
32 bits
• Received clock supplied by the PHY
• External transmit clock source.
Bus Width
Host System
19.44 MHz
77.76 MHz
38.88 MHz
155.52 MHz
77.76 MHz
POSIC
Clock Frequency
Data
OC-3/STM-1
OC-12/STM-4
OC-12/STM-4
OC-48/STM-16
OC-48/STM-16
SONET/SDH
CY7C9536B
Line Rate
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