CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 32

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Reset Requirements
Asserting the RST_n signal will asynchronously reset all
sequential elements of POSIC2GVC. Even though the reset is
treated as asynchronous signal, it is recommended that a
minimum of 1-ms-wide active LOW RST_n is applied after all
power supplies have stabilized.
Power-Up Requirements
When HSTL I/O is used, V
powered up first before V
up at least 300ms after the last of the other power supplies.
Table 6. POSIC2GVC Pin Timing Requirements
AC Specifications
Table 7. Line Interface Timing Parameter Values
Line Interface
Overhead Bytes
Access – Serial Ports
Memory Interface
System Interface
Host CPU Interface
f
t
t
t
t
t
t
t
t
t
t
f
t
t
t
Notes:
21. The parameter is guaranteed by design and is not tested during production.
22. The parameter is guaranteed by characterization and is not tested during production.
TS
TXCLKIP
TXCLKID
TXCLKP
TXCLKD
TXCLKR
TXCLKF
TXDO
TXFPO
PAROUTO
TXFPPW
RS
RXCLKP
RXCLKOD
RXCLKR
[21]
Parameter
[21]
POSIC2GVC
Pin Group
[21]
[22]
[21]
[22]
[21]
[22]
[21]
[21]
TXCLKOUT, TXCLKI Frequency (must be frequency coherent to
RXCLK when used as the transmit PLL clock source).
f
MHz; depends on the Bus Width and Line Rate used.
TXCLKI Period
TXCLKI Duty Cycle
TXCLKOUT Period
TXCLKOUT Duty Cycle
TXCLKOUT Rise Time
TXCLKOUT Fall Time
TXD Output Delay after ↑ of TXCLKOUT
TXFRAME_PULSE Output Delay after ↑ of TXCLKOUT
SONETTX_PAROUT Output Delay after ↑ of TXCLKOUT
TXFRAME_PULSE Width
RXCLK Frequency
f
19.44 MHz; depends on the Bus Width and Line Rate used.
RXCLK Period
RXCLK Duty Cycle
RXCLK Rise Time
TS
RS
nominal (f
16-/8-bit HSTL/single-ended LVPECL
interface
LVTTL
LVTTL
UTOPIA Level 3/
OIF-SPI Level3
HBST
16-/32-bit CPU Interface LVTTL
nominal (f
Peripheral Device/Bus Standard
CC5
CC1
supply. V
, V
TSN
RS
CC2
N) can be 155.52 MHz, 77.76 MHz, 38.88 MHz,
) can be 155.52 MHz, 77.76 MHz, 38.88 MHz, 19.44
, and V
CC5
shall be powered
CC3
Description
CONFIDENTIAL
need to be
CY7C1370B/C or
CYS25G0101DX
CY7C1464V33
(min. 200-MHz grade)
Compatible with
Intel/Motorola CPUs
Compatible/Suggested
There is no particular power-up sequence requirements
among V
There is no particular power-up sequence requirements
among V
RST_n needs to be activated until all the power supplies have
stabilized.
AC and Timing Specifications
The POSIC2GVC device interfaces to industry standard
peripheral devices or buses. Hence the POSIC2GVC pin
timing parameters are governed by the interface requirements
of the peripherals or the relevant standards. Table 6 details the
timing requirements.
Part Number
CC1
CC1
, V
, V
CC2
CC2
, and V
, V
1/(f
CC3
(1 – 0.65%)
1/(f
1/(f
(1 – 0.65%)
Refer PHY data sheet
Described in this document
Compatible to NoBL™ or equivalent
memory chip
ATM Forum: BTD-PHY-UL3-01.05
Saturn Group: PMC-980495 Issue
Described in this document
f
f
RS
TS
TS
, and V
RSN
Min.
TSN
CC3
0.3
0.3
0.5
0.5
0.5
43
43
40
6
–
max.)
max.)
max.)
*
*
in this case.
Reference/Remarks
CC5
if HSTL I/O is not used.
(1 + 0.65%)
(1 + 0.65%)
1/(f
1/(f
1/(f
CY7C9536B
f
f
Max.
RS
TSN
TS
TS
RSN
1.5
1.5
4.5
4.5
4.5
1.5
57
60
55
57
min.)
min.)
min.)
*
*
Page 32 of 46
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%