CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 6

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
In the receive direction, GFP frames are delineated based on
the length-CRC construct pair header, integrity verified,
payload extracted, optionally descrambled and sent to the
Programmable Frame Tagging Engine.
Any selected VC channel can be programmed to become a
‘clear channel’. The encapsulator and decapsulator remain in
transparent mode for the clear channel and data passes
through without any modification. This feature can be used to
transport any raw data streams on a portion of bandwidth while
the rest of the bandwidth is utilized for protocol traffic.
Programmable Frame Tagging Engine
The Programmable Frame Tagging Engine provides preclas-
sification of the packets/frames at the wire rate. This helps in
utilizing the link layer device more efficiently.
The Programmable Frame Tagging Engine enables the user
to perform preclassification of all the incoming packets into
one of the 16 possible categories. Since each channel can
have up to 16 different categories, and up to 16 virtual concat-
enated channels are possible, this engine supports up to 256
different categories. For classification, two-pass comparison
can be specified. For each comparison a field of up to six bytes
can be selected within the first 64 bytes of the packet and
compared with up to 16 programmed values. The comparison
is on a bit by bit basis and any bit comparison can be masked
with a user programmable mask register. A four-bit tag is
attached to the cell/packet, based on the match. Host CPU can
program these parameters through register programming.
The following drawing demonstrates one possible combi-
nation of classification with the help of the Programmable
Frame Tagging Engine.
Deframer
SONET/
SONET/
Framer
SDH
SDH
Concatenation
Concatenation
Virtual
Virtual
Protocol/Frame Types
"Clear Channel Transport"
Figure 3. Protocol Framers
CONFIDENTIAL
ATM Deframer
GFP Protocol
GFP Protocol
ATM Framer
Deframer
Deframer
"Clear Channel Transport"
Framer
Framer
HDLC
HDLC
2) Selected VC channels can be declared "clear
1) Only one framer/deframer active
The following functions can be achieved with the help of the
Programmable Frame Tagging Engine:
SONET/SDH Bypass
POSIC2GVC supports the SONET/SDH framer/deframer
bypass mode. Host CPU can program such bypass. In this
mode, the data frames/packets, encapsulated by one of the
encapsulators, will be transmitted transparently through VC
and SONET/SDH blocks to the fiber side and vice versa.
System Interface
The system interface is programmable. For application in an
ATM system, POSIC2GVC system interface can be
programmed to be PHY side interface as per UTOPIA level 3
specifications.
For variable length packets, POSIC2GVC system interface
can be programmed to be OIF-SPI level 3. ATM cells can also
be transferred over OIF-SPI level 3 bus.
System interface can be programmed in HBST mode. In this
case, a separate set of address pins are supported on the
system side. This mode supports high-speed burst access.
channel transport"
• Incoming packet analysis to parse packets/frames/cells at
• User-programmable routing of control packets to CPU for
• Incoming frames tagged based on bits (such as congestion)
• User-programmable offset to locate Ethernet and other
wire speed.
processing.
in incoming packets.
frames within DOS and other proprietary MAN networking
protocols to allow MPLS processing.
Tagger
Frame
UTOPIA
SPI-3/
UTOPIA
SPI-3/
CY7C9536B
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