CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 19

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
AD [18:0]
WE
ADV/LD
CE1
CE2
CE3
OE
DQ1[31:0]
DQ2 [31:0]
CpuClk
CpuSel
CpuTs_n/CpuAds_n
CpuWrRd
Memory Interface for Virtual Concatenation
CPU Interface Signals
Signal Name
(continued)
I/O
I/O LVTTL
I/O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Pad Type
19
1
1
1
1
1
1
32
32
1
1
1
1
Pins JTAG
CONFIDENTIAL
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Synchronous Address Inputs
Used to address up to six 512k x 36 NoBL™ SRAMs.
Sampled at the rising edge of the CLK.
Synchronous Write Enable Input, active LOW.
This must be sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence
Synchronous Advance/Load Input
This pin is used to advance the on-chip (SRAM’s) address counter or
load a new address. When HIGH (and CEN is asserted LOW) the
internal burst counter of SRAM is advanced. When LOW, a new
address is loaded into the SRAM for an access.
After being deselected, ADV/LD should be driven LOW in order to load
a new address.
Synchronous Chip Enable 1, active LOW.
Sampled on the rising edge of CLK. Used to select/deselect first bank
of the NoBL memory.
Synchronous Chip Enable 2, active LOW.
Sampled on the rising edge of CLK. Used to select/deselect second
bank of the NoBL memory.
Synchronous Chip Enable 3, active LOW.
of the NoBL memory.
Asynchronous Output Enable, permanently active LOW.
This pin is internally grounded to the VSS2 bus.
The pin should be connected to the OEN input of the NoBL memories,
or alternatively, left unconnected if the NoBL OEN input is directly
grounded on the board.
Synchronous Bidirectional Data I/O lines for SRAM1.
As inputs to SRAM, these pins feed into a data register that is triggered
by the rising edge of CLK. As outputs from SRAM, they deliver the data
contained in the memory location specified by A [18:0] during the
previous clock rise of the read cycle. When OE is asserted LOW, the
pins can behave as outputs from SRAM. When HIGH, DQ1 [31:0] are
placed in a three-state condition by the SRAM. The outputs are
automatically three-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
Synchronous Bidirectional Data I/O lines for SRAM2.
As inputs to SRAM, these pins feed into a data register that is triggered
by the rising edge of CLK. As outputs from SRAM, they deliver the data
contained in the memory location specified by A [18:0] during the
previous clock rise of the read cycle. When OE is asserted LOW, the
pins can behave as outputs from SRAM. When HIGH, DQ2 [31:0] are
placed in a three-state condition by the SRAM. The outputs are
automatically three-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
CPU Clock.
Used to select between Intel and Motorola CPU.
‘0’ = Motorola, ‘1’ = Intel
Transfer Start. Active LOW
Write/Read Signal. In Intel mode, active HIGH for write operation. In
Motorola mode, active LOW for write operation.
Sampled on the rising edge of CLK. Used to select/deselect third bank
Pin Description
CY7C9536B
Page 19 of 46