CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 14

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
RERR
REOP
RSOP/RSOC
RCA
RSX
Signal Name
(continued)
I/O
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
Pad Type
1
1
1
1
1
Pins JTAG
CONFIDENTIAL
N
N
N
N
N
POS:
Receive error indicator (RERR) signal.
RERR is used to indicate that the current packet is aborted and should
be discarded. RERR shall only be asserted when REOP is asserted.
Conditions that can cause RERR to be set may be, but are not limited
to, FIFO overflow, abort sequence detection and FCS error.
RERR is considered valid only when RVAL is asserted.
HBST:
Receive error indicator (RERR) signal.
A HIGH indicates the current packet or cell has error.
POS:
Receive End Of Packet (REOP) signal.
REOP is used to delineate the packet boundaries on the RDAT bus.
When REOP is HIGH, the end of the packet is present on the RDAT
bus.
REOP is required to be present at the end of every packet and is
considered valid only when RVAL is asserted.
HBST:
End of Packet/cell (REOP) signal.
A high indicates the end of packet or cell.
POS:
Receive Start of Packet (RSOP) signal.
RSOP is used to delineate the packet boundaries on the RDAT bus.
When RSOP is HIGH, the start of the packet is present on the RDAT
bus.
RSOP is required to be present at the start of every packet and is
considered valid when RVAL is asserted.
ATM:
Receive start of cell (RxSOC).
This signal marks the start of a cell structure on the RxData bus.
The first word of the cell structure is present on the RxData[31:0] bus
when RxSOC is HIGH.
RxSOC is updated on the rising edge of RxClk.
HBST:
Receive Start of Packet/cell (RSOP) signal.
A HIGH indicates start of packet or start of cell.
ATM:
UTOPIA Receive Cell Available (RxClav).
RxClav will be asserted, whenever a minimum of 1 cell of data is
available in the Receive FIFO.
HBST:
Receive FIFO available (RSTFA) signal.
RSTFA indicates when data is available in the receive FIFO. RSTFA
will be asserted, whenever receive FIFO has at least predefined
number of bytes to be read (the number of bytes is user program-
mable).
RSTFA is updated on the rising edge of RCLK.
POS:
Receive start of transfer signal.
RSX indicates when the in-band port address is present on the RDAT
bus. When RSX is HIGH and RVAL is LOW, the value of RDAT[7:0] is
the address of the receive FIFO to be selected by POSIC2GVC.
Subsequent data transfers on the RDAT bus will be from the port as
specified by the in band address.
Pin Description
CY7C9536B
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