CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 18

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
STPA
PTCA
TSX
Signal Name
(continued)
I/O
O LVTTL
O LVTTL
I
LVTTL
Pad Type
1
1
1
Pins JTAG
CONFIDENTIAL
N
N
N
POS:
Selected Channel Transmit Packet Available (STPA) signal. STPA
transitions HIGH when a predefined minimum number of bytes are
available in the selected transmit FIFO. Once HIGH, STPA indicates
that transmit FIFO is not full. When STPA transitions LOW, it optionally
indicates that transmit FIFO is full or near full (user programmable).
STPA always provides status indication for the selected channel in
order to avoid FIFO overflows while polling is performed.
STPA is three-stated when TENB is deasserted in the previous cycle.
STPA is also deasserted when either the null-port address (0x1F) or
an address not matching the POSIC2GVC address is presented on
the TADR[3:0] signals when TENB is sampled HIGH (has been
de-asserted during the previous clock cycle).
STPA is mandatory only if packet-level transfer mode is supported. It
is not be driven in byte-level mode.
ATM:
There is no corresponding pin definition in ATM mode, however, this
pin will output the same signal as STPA in POS mode
HBST:
FIFO Available Status (TSTFA) signal.
FIFO available status of the selected port is reflected on this pin two
clocks after detecting the port address when the TDVAL signal is
active.
POS:
Polled-Port Transmit Packet Available (PTPA) signal.
PTPA transitions HIGH when a predefined (user-programmable)
minimum number of bytes are available in the polled transmit FIFO.
Once HIGH, PTPA indicates that the transmit FIFO is not full. When
PTPA transitions LOW, it optionally indicates that transmit FIFO is full
or near full (user-programmable). PTPA allows polling the
POSIC2GVC channel selected by TADR[3:0] when TENB is asserted.
PTPA is driven by a POSIC2GVC when its address is polled by
TADR[3:0]. POSIC2GVC will three-state PTPA when either the
null-port address (0x1F) or an address not matching POSIC2GVC is
provided on TADR[3:0].
PTPA is mandatory only if in packet-level transfer mode. It will not be
driven in byte-level mode.
ATM:
UTOPIA Transmit Cell Available (TxClav)
The TxClav signal indicates when a cell is available in the transmit
FIFO for the port polled by TxAddr[3:0] when TxEnb* is asserted.
When HIGH, TxClav indicates that the corresponding transmit FIFO
is not full and a complete cell may be written. When TxClav goes LOW,
it can be configured to indicate either that the corresponding transmit
FIFO is near full or that the corresponding transmit FIFO is full. TxClav
is three-stated when either the null-Port address (0x1F) or an address
not matching the address space set is latched from the TxAddr[4:0]
inputs when TxEnb* is HIGH.
TxClav is updated on the rising edge of TxClk.
HBST:
FIFO Available status on TFAST bus (TSOFST) signal.
Active HIGH pulse indicates the start of FIFO available status on
TFAST bus. This signal is repeated once in every four clocks.
POS:
Transmit Start of Transfer (TSX) signal.
TSX indicates inband port address on the TDAT bus. When TENB is
HIGH and TSX is asserted (HIGH), the value of TADR[3:0] is the
address of transmit FIFO selected.
TSX is valid only when TENB is deasserted.
Pin Description
CY7C9536B
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