LH28F400BVE-TL85 Sharp Electronics, LH28F400BVE-TL85 Datasheet - Page 9

• Manufacturer Part Number: LH28F400BVE-TL85
• Manufacturer: Sharp Electronics

Specifications of LH28F400BVE-TL85

• Cell Type: NOR
• Density: 4Mb
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F400BVE-TL85 SmartVoltage Flash memory
includes an on-chip WSM to manage block erase and
word/byte write functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block erasure
and word/byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
word/byte writing. All functions associated with altering
memory contents−block erase, word/byte write, status and
identifier codes−are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
PP
enables successful block erasure and
PP
voltage. High
2.1 Data Protection
Depending on the application, the system designer may
choose to make the V
(available only when memory block erases or word/byte
writes are required) or hardwired to V
accommodates either design practice and encourages
optimization of the processor-memory interface.
When V
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to V
write functions are disabled when V
lockout voltage V
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and word/byte write operations.
Refer to Table 6 for write protection alternatives.
3DFFF
3CFFF
3FFFF
3EFFF
3BFFF
3AFFF
2FFFF
1FFFF
0FFFF
3E000
3D000
3C000
3B000
3A000
39FFF
38FFF
37FFF
27FFF
17FFF
07FFF
3F000
39000
38000
30000
28000
20000
18000
10000
08000
00000
PP
V
PPLK
Figure 3. Memory Map
LKO
, memory contents cannot be altered.
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
or when RP# is at V
4K-word Boot Block
4K-word Boot Block
Top Boot
PP
power supply switchable
CC
PPH1/2/3
is below the write
IL
. The device’s
. The device
0
1
2
3
4
5
0
1
0
1
2
3
4
5
6
Rev. 1.02
PP
. All