LH28F400BVE-TL85 Sharp Electronics, LH28F400BVE-TL85 Datasheet - Page 22

• Manufacturer Part Number: LH28F400BVE-TL85
• Manufacturer: Sharp Electronics

Specifications of LH28F400BVE-TL85

• Cell Type: NOR
• Density: 4Mb
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 RY/BY#, Block Erase and Word/Byte
RY/BY# is a full CMOS output that provides a hardware
method of detecting block erase and word/byte write
completion. It transitions low after block erase or
word/byte write commands and returns to V
WSM has finished executing the internal algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also V
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
Write Polling
OH
when the device is in block erase suspend
OH
when the
(with word/byte write inactive), word/byte write suspend
or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between V
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V
supply traces and decoupling will decrease V
spikes and overshoots.
PP
Trace on Printed Circuit Boards
PP
Power supply trace. The V
CC
and GND and between its V
CC
CC
power bus. Adequate V
and GND. The bulk
PP
Rev. 1.02
voltage
PP
pin
PP
PP