FIN324CMLX Fairchild Semiconductor, FIN324CMLX Datasheet - Page 8

• Manufacturer Part Number: FIN324CMLX
• Description: IC SER DES 24BIT ULP 40-MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN324CMLX

• Function: Serializer/Deserializer
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 24
• Number Of Outputs: 24
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Output Current: 10 mA
• Minimum Operating Temperature: - 30 C
• Resolution: 320 x 240
• Supply Current: 5 uA
• No. Of Inputs: 24
• No. Of Outputs: 24
• Supply Voltage Range: 2.5V To 3V, 1.6V To 3V
• Driver Case Style: MLP
• No. Of Pins: 40
• Termination Type: SMD
• Operating Temperature Range: -30°C To +85°C
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Digital Ic Case Style: MLP
• Frequency: 15MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Details

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.1.4
Applications Diagrams
Figure 6.
Figure 7.
Hsync_ADDR
Baseband
Processor
R,G,B[5:0]
Baseband
Processor
Hsync_D/C
CKSEL
GPIO
R,G,B[5:0]
RESET
/STBY
/RES
Vsync
PCLK
CKSEL
GPIO
RESET
/STBY
/WE
/CS
Vsync
/RES
SD
PCLK
OE
/CS
SD
OE
Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display
Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display
VDDP1
VDDP1
D4:G6
Notes:
D4:G6
C4
C3
D3
G3
G2
A4
B4
A3
B3
A2
B2
A1
F3
B1
Notes:
G3
G2
1.
2.
3.
4.
5.
A4
B4
C4
C3
A3
B3
A2
B2
A1
D3
B1
F3
STRB0
STRB1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
VDDP VDDS/A
VDDP1
C2
1. Write-only Interface.
2. Unused slave output pin must be NC (No Connection).
3. /CS used to strobe sub-display data.
4.
5.
Write-only Interface.
Unused slave output pin must be NC (No Connection).
/WE used to strobe sub-display data.
PCLK used for RGB mode
Pin numbers for BGA package.
VDDP VDDS/A
STRB0
STRB1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
VDDP1
C2
Master
PCLK used for RGB mode
Pin numbers for BGA package.
Master
VDDS/A
E2
CKS-
CKS+
GND
GND
GND
DS+
VDDS/A
E2
DS-
CKS-
CKS+
F2
GND
GND
GND
DS+
DS-
F2
D1
E1
G1
F1
D2
C1
E3
D2
C1
D1
E1
G1
F1
E3
.
D2
C1
E3
G1
F1
D1
E1
.
G1
F1
D1
E1
D2
C1
E3
8
GND
GND
GND
C2
VDDP VDDS/A
CKS+
CKS-
DS+
DS-
VDDP2
GND
GND
GND
C2
CKS+
CKS-
DS+
DS-
VDDP2
VDDP VDDS/A
Slave
DP[17:0]
PAR/SPI
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
WCLK0
WCLK1
Slave
E2
SLEW
VDDS/A
PAR/SPI
VDDP
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
/RES
WCLK0
WCLK1
R/W
M/S
E2
SLEW
VDDP
VDDS/A
/RES
F2
R/W
M/S
F2
A4
B4
D4:G6
C4
C3
A3
B3
A2
B2
A1 NC
D3
F3
G3
G2
B1
A4
B4
D4:G6
C4
C3
A3
B3
A2
B2
A1 NC
D3
F3
G3
G2
B1
NC
VDDP2
VDDP
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
2
Data
ADDR
/WE
RESET
P/S
/CS
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
OE
Main Display
Sub- Display
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
Data [7:0]
D/C
/CS
RESET
P/S
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
OE
Main Display
Sub- Display
[
7:0
]
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