FIN324CMLX Fairchild Semiconductor, FIN324CMLX Datasheet - Page 13

• Manufacturer Part Number: FIN324CMLX
• Description: IC SER DES 24BIT ULP 40-MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN324CMLX

• Function: Serializer/Deserializer
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 24
• Number Of Outputs: 24
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Output Current: 10 mA
• Minimum Operating Temperature: - 30 C
• Resolution: 320 x 240
• Supply Current: 5 uA
• No. Of Inputs: 24
• No. Of Outputs: 24
• Supply Voltage Range: 2.5V To 3V, 1.6V To 3V
• Driver Case Style: MLP
• No. Of Pins: 40
• Termination Type: SMD
• Operating Temperature Range: -30°C To +85°C
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Digital Ic Case Style: MLP
• Frequency: 15MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Details

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.1.4
AC Deserializer Specifications
AC Data Latencies
AC Oscillator Specifications
AC Reset and Standby Timing
t
t
Symbol
t
t
t
STRB-STBY
t
t
t
t
t
t
OSC-STBY
STRB-RES
t
PWL-WR0
PWL-WR1
t
t
t
PDV-WR0
PDV-WR1
t
t
t
t
t
OSC-RES
VDD-OFF
RES-OFF
PWL-SPI
t
PDV-RD
PDV-SPI
PWL-RD
PD-WR0
PD-WR1
t
PD-RDC
PD-RDD
R0
R1
PD-SPI
PD-RD
f
t
OSC
CS
, t
, t
F0
F1
Output Edge Rates of
WCLK0,WCLK1
Output Edge Rates of R/W,
DP[17:0] CNTL[5:0]
CNTL[5:0],R/W to Falling
Edge of WCLKn
DP, CNTL to WCLK0 ↑
DP, CNTL to WCLK1 ↑
CNTL to WCLKn ↑
Data, CNTL to SCLK ↑
WCLK0 Pulse Width Low;
Write Mode
WCLK1 Pulse Width Low;
Write Mode
Pulse Width Low of WCLK;
Read Mode
Pulse Width Low of WCLK;
SPI Mode
Write Latency
Write Latency
Total Read Latency
Read Control Latency
Read Data Latency
SPI Write Latency
Serial Operating Frequency
Oscillator Stabilization Time
After Standby
Oscillator Stabilization Time
After Reset
Power Down Relative to
/RES
/RES after last STRBn ↑
Standby time after last
strobe
Master/Slave Reset Disable
Time
(15)
Parameter
SLEW=0, CL=5pF 20% to 80%
SLEW=1, C
SLEW=0, C
SLEW=1, C
M/S=0
Figure 15
PAR/SPI=1
PAR/SPI=1
PAR/SPI=1
PAR/SPI=0
M/S=0, R/W=0, PAR/SPI=1
Figure 15
M/S=0, R/W=0, PAR/SPI=1
Figure 15
M/S=0, R/W=1, PAR/SPI=1
Figure 17
M/S=0, R/W=0, PAR/SPI=0
Figure 16
WRITE Mode, CKSEL=0
Figure 15
WRITE Mode, CKSEL=1
Figure 15
READ Mode
Figure 17
READ Mode
Figure 17
READ Mode
Figure 17
SPI-WRITE Mode
Figure 16
V
/RES=1, /STBY ↑ Transition
V
/STBY=1, /RES ↑ Transition
Figure 19
M/S=1, /STBY=1, R/W=0
Figure 19
M/S=1, /STBY=1
Figure 19
M/S=1 /STBY=1, /RES=↓
Figure 19
DDA
DDA
=V
=V
(5)
DDS
DDS
, C
Test Conditions
=2.75V
=2.75V
L
(5)
(5)
(5)
(5)
L
L
L
=5pF 50% to 50%
(8,10,11)
(8,10,12)
(8,10,13)
=5pF 20% to 80%
=5pF 20% to 80%
=5pF 20% to 80%
, Figure 15
, Figure 15
, Figure 17
, Figure 16
13
(17)
(8,10,14)
(8,9,10)
(8,9,10)
(16)
(5,7)
(5,7)
(5,7)
(5,7)
(5)
(5)
(5)
(5)
(5)
Min.
200
200
240
200
50
18
40
50
18
40
20
8
8
0
0
Typ.
224
220
147
111
340
276
115
275
60
24
60
56
20
56
84
15
30
15
4
Max.
480
310
17
10
22
17
30
50
20
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Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs