FIN324C Fairchild Semiconductor, FIN324C Datasheet
FIN324C
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FIN324C Summary of contents
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... Resolution © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Description The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system ...
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... Typical Application Diagram WE/PCLK 2 Baseband / Microprocessor Data/Control 24 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Range Package Description 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch CKS ...
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... Note: 1. Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Description of Signals Master/Slave Control Input: The master is tied to the processor. The slave is tied to the display(s). M/S=1 MASTER, M/S =0 SLAVE Reset and power-down signal ...
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... CNTL[4] A R/W CNTL[2] or SDAT CNTL[5] B CKSEL CNTL[3] or SCLK C GND VDDP CNTL[1] D CKS+ GND M/S E CKS- VDDS GND F DS- VDDA PAR/SPI G DS+ /RES /STBY © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 DP[16] VDDP 30 DP[15] DS+ 29 DP[14] DS- 28 DP[13] VDDS 27 DP[12] VDDA 26 VDDP CKS- 25 DP[11] CKS+ 24 DP[10] /RES 23 DP[9] 22 PAR/SPI DP[8] M/S 21 MLP Pin Assignments (40 Pins, 6x6mm, .5mm Pitch, Top View) 42 FBGA Package 3 ...
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... STRB0 1 1 STRB1 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 (/RES, /STBY) Reset and Standby Mode Functionality: Reset and standby mode functionality is determined by the state of the /RES and /STBY signals for the master device and the /RES and internal standby-detect signal for the slave device ...
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... B Master A Figure 4. BGA Pair © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Parallel I/O Signals The parallel data port signals consist of the DP[17:0], CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals. These signals have built-in voltage translation, allowing the signals of the master and slave to be connected to or ...
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... STRB0 are serialized. STRB0 should be connected to the SPI mode chip select. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Slave Deserializer Operation (Read-Control Phase) 1. Captures data from serial transfer. 2. Internally decodes that this is a READ transaction. ...
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... A1 VDDP1 GPIO /STBY G2 /RES B1 CKSEL Notes: Figure 7. Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Master Slave VDDP2 VDDP1 VDDS VDDP VDDS/A VDDP VDDS/A A4 WCLK0 STRB0 B4 STRB1 ...
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... B2 A1 R/W VDDP1 D3 GPIO F3 G3 /STBY G2 /RES B1 CKSEL Notes: Figure 9. R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 (Continued) Master Slave VDDP2 VDDS/A VDDP1 VDDS VDDP VDDS/A VDDP VDDS/A WCLK0 STRB0 STRB1 ...
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... Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales rep, or contact Fairchild directly at © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 (Continued) Master Slave VDDP2 ...
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... DDA DDS V Supply Voltage DDP T Operating Temperature A Note and V supplies must be hardwired together to the same power supply. V DDA DDS DDA DDS © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Parameter Parameter Min. 2.5 1.6 -30 11 Min. Max. Unit -0.5 +3.6 V -0.5 V +0.5 V DDP -65 150 °C +150 ° ...
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... Write Mode Hold Time H1 t READ Mode Setup Time S2 t READ Mode Hold Time H2 CKSEL to STRBn Setup t S-STRB Time © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Test Conditions SLEW -250µA OH SLEW -1mA OH SLEW 250µA OL SLEW 1mA OL Slave Relative to Master 5 ...
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... VDD-OFF /RES /RES after last STRBn ↑ t STRB-RES t Standby time after last strobe STRB-STBY Master/Slave Reset Disable t RES-OFF Time © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Test Conditions (4) SLEW=0, CL=5pF 20% to 80% (4) SLEW=1, C =5pF 20% to 80% L (4) SLEW=0, C =5pF 20% to 80% L (4) SLEW=1, C ...
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... HIGH recommended that /RES be held low during the power supply ramp. 20. STRBn must be held off until internal oscillator has stabilized. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Test Conditions DDP Figure 18 (19) M/S=0 /STBY=1, /RES=↑ ...
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... CKSEL Write Setup Time STRBn CKS DS t PD-WRn DP CNTL WCLKn t CSn Setup: CKSEL R/W=0, PAR/SPI=1 Figure 15. Slave Write Mode Timing © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Setup Time STRBn Data CNTL,R/W Hold Time t H1 STRBn CNTL,R/W Setup: CKSEL R/W=1 Figure 12 ...
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... Typical Performance Characteristics STRBn CKS DS CNTL SLV WCLKn] DP SLV DP MSTR Setup: CKSEL R/W=1, PAR/SPI=1 DP[23:0],R/W STRBn Deserializer VDDP VDDS/A /RES /STBY STROBE Deserializer © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 (Continued) t PD-RD t PD- L-RD n CSn t PDV-RD n Figure 17. Slave Read Mode Timing VDDP t VDD-SKEW VDDS/A t ...
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... Physical Dimensions © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 (DATUM A) Figure 20. 40-Lead, Molded Leadless Package (MLP) 17 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 Figure 21. 42-Ball, Ball Grid Array (BGA) Package 18 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FIN324C Rev. 1.0.9 19 www.fairchildsemi.com ...