FIN324CMLX Fairchild Semiconductor, FIN324CMLX Datasheet - Page 6

• Manufacturer Part Number: FIN324CMLX
• Description: IC SER DES 24BIT ULP 40-MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN324CMLX

• Function: Serializer/Deserializer
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 24
• Number Of Outputs: 24
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Output Current: 10 mA
• Minimum Operating Temperature: - 30 C
• Resolution: 320 x 240
• Supply Current: 5 uA
• No. Of Inputs: 24
• No. Of Outputs: 24
• Supply Voltage Range: 2.5V To 3V, 1.6V To 3V
• Driver Case Style: MLP
• No. Of Pins: 40
• Termination Type: SMD
• Operating Temperature Range: -30°C To +85°C
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Digital Ic Case Style: MLP
• Frequency: 15MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Details

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.1.4
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild’s
proprietary differential CTL I/O technology. During data
transfers, the serial I/O are powered up to a normal
operating mode around .5V. Upon completion of a data
transfer, the serial I/O goes to a lower power mode
around V
Serial I/O Orientation Logic
Table 7. Serial Pin Orientation
G
E
D
C
B
A
F
Package
6
MLP
BGA
Master
BGA
5
DDS
4
.
3
CKS+
CKS-
Figure 4.
DS+
DS-
2
CKS+
1
D1
2
Master (M/S=1) (Pad/Pin #)
1
BGA Pair
<DS+>
<DS->
<CKS->
<CKS+>
CKS-
2
E1
3
3
4
Slave
BGA
5
DS-
6
F1
6
A
D
E
B
C
F
G
21
22
23
24
25
26
27
28
29
30
6
DS+
The serial I/O signal traces should not cross between
the master and the slave. The pin locations have been
designed to eliminate the need to cross traces. See
Table 7, Figure 4, and Figure 5.
G1
Master
7
MLP
CKS+
CKSEL(H)
PAR/SPI
G1
VDD S
VDDA
CKS+
7
CKS-
/RES
DS+
M/S
DS-
Figure 5.
10
9
8
7
6
5
4
3
2
2
1
Slave (M/S=0) (Pad/Pin #)
CKS-
F1
6
MLP Pair
1
2
3
4
5
6
7
8
9
10
CKSEL(H)
(DS+)
(DS-)
VDD S
VDD A
(CKS-)
(CKS+)
/RES
PAR/SPI
M/S
DS-
E1
3
www.fairchildsemi.com
Slave
MLP
DS+
D1
2
30
29
28
27
26
25
24
23
22
21