FIN324CMLX Fairchild Semiconductor, FIN324CMLX Datasheet - Page 5

• Manufacturer Part Number: FIN324CMLX
• Description: IC SER DES 24BIT ULP 40-MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN324CMLX

• Function: Serializer/Deserializer
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 24
• Number Of Outputs: 24
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Output Current: 10 mA
• Minimum Operating Temperature: - 30 C
• Resolution: 320 x 240
• Supply Current: 5 uA
• No. Of Inputs: 24
• No. Of Outputs: 24
• Supply Voltage Range: 2.5V To 3V, 1.6V To 3V
• Driver Case Style: MLP
• No. Of Pins: 40
• Termination Type: SMD
• Operating Temperature Range: -30°C To +85°C
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Digital Ic Case Style: MLP
• Frequency: 15MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Details

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.1.4
System Control Pins
(M/S) Master / Slave Selection: A given device can be
configured as a master or slave device based on the
state of the M/S pin.
Table 1. Master/Slave
(PAR/SPI) SPI Mode Selection: The PAR/SPI signal
configures STRB0(WCLK0) for SPI mode write operation.
STRB1(WCLK1) always operates in parallel mode.
Control signals CNTL[5:0] all pass in SPI mode. In SPI
mode, the SCLK signal is used to strobe the serializer.
SPI mode supports SPI writes only.
Table 2. Channel 0 PAR/SPI Configuration
(CKSEL) Strobe Selection Signal: The CKSEL signal
exists only on the master device and determines which
strobe signal is active. The active strobe signal is
selected by CKSEL and PAR/SPI inputs.
Table 3. PAR/SPI
(/RES, /STBY) Reset and Standby Mode Functionality:
Reset and standby mode functionality is determined by
the state of the /RES and /STBY signals for the master
device and the /RES and internal standby-detect signal
for the slave device. The /RES control signal has a filter
that rejects spurious pulses on /RES.
Table 4. Reset and Standby Modes
Note:
2.
PAR
PAR
/SPI
/SPI
/RES
0
1
0
0
1
1
0
1
1
The slave device is put into standby mode through
control signals sent from the master device.
M/S=1 MASTER
CKSEL
SDAT=CNTL[4]
SCLK=CNTL[5]
/STBY
Parallel Mode
/CS=STRB0
M/S
0
1
0
1
SPI Mode
0
1
X
0
1
(2)
Reset Mode
CNTL[5]
Source
Master
Strobe
STRB1
STRB0
STRB1
Operating
Standby
Master
Mode
Mode
SDAT=DP[7] & CNTL[4]
SCLK=DP[6] & CNTL[5]
Configuration
M/S=0 SLAVE
Parallel Mode
Master Mode
/CS=WCLK0
Slave Mode
SPI Mode
DP[6] & CNTL[5]
Slave Strobe
Reset Mode
WCLK1
WCLK0
WCLK1
Source
Operating
Standby
Mode
Slave
Mode
(2)
5
Table 5. Reset and Standby Mode States
(SLEW) Slew Control: The slew control operates only
when in slave mode. This signal changes the edge rate
of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0
signals to optimize edge rate for the load being driven.
Master read mode outputs have “slow” edge rates. See
the AC Deserializer Specifications table for “slow” and
“fast” edge rates.
Table 6. Slew Rate Control
CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES,
/STBY(SLEW), PAR/SPI, and CKSEL. For connectivity
flexibility, these signals are over-voltage tolerant to the
maximum supply voltage connected to the device. This
allows these signals to be tied HIGH to either a V
V
signals are all CMOS inputs and should never be
allowed to float.
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0],
CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals.
These signals have built-in voltage translation, allowing
the signals of the master and slave to be connected to
different V
DP[17:0]
CNTL[5:0]
STRB[0:1]
(WCLK[0:1])
DDP
Pin
supply without static current consumption. These
/STBY (SLEW)
DDP
0
1
supply voltages.
Reset / Standby
Disabled
Disabled
Disabled
Master
Slave M/S=0
Reset
Slave
High
Low
Low
“Slow”
“Fast”
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Last Data
Last Data
Standby
Slave
High
DDS
or