SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 94

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
10.2.19 Subaddress 12h
Table 55:
Table 56:
The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]].
Bit
D3
D[2:0]
RTS0 output
3-state
Constant LOW
CREF (13.5 MHz toggling pulse; see
CREF2 (6.75 MHz toggling pulse; see
HL; horizontal lock indicator
VL; vertical and horizontal lock:
DL; vertical and horizontal lock and color detected:
Reserved
HREF, horizontal reference signal; indicates 720 pixels
valid data on the expansion port. The positive slope
marks the beginning of a new active line. HREF is also
generated during the vertical blanking interval
(see
HS:
HQ; HREF gated with VGATE
Reserved
V123; vertical sync (see vertical timing diagrams
Figure 24
VGATE; programmable via VSTA[8:0] 17h[0] 15h[7:0],
VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]]
LSBs of the 9-bit ADCs
FID; position programmable via
VSTA[8:0] 17h[0] 15h[7:0]; see vertical timing diagrams
Figure 24
HL = 0: unlocked
HL = 1: locked
VL = 0: unlocked
VL = 1: locked
DL = 0: unlocked
DL = 1: locked
Programmable width in LLC8 steps via
HSB[7:0] 06h[7:0] and HSS[7:0] 07h[7:0]
Fine position adjustment in LLC2 steps via
HDEL[1:0] 11h[5:4] (see
Figure
and
and
Description
polarity of RTS0 output
signal
luminance delay
compensation (steps in
2/LLC)
Mode/delay control; 11h[7:0]
RT signal control: RTS0 output; 12h[3:0]
26).
Figure
Figure 25
25)
Rev. 03 — 17 January 2006
Figure
[1]
:
26)
Figure
Figure
Symbol
RTP0
YDEL[2:0]
…continued
26)
26)
Value Function
0
1
100
000
011
RTSE03 RTSE02 RTSE01 RTSE00
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PAL/NTSC/SECAM video decoder
non-inverted
inverted
...0...
...3
4...
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SAA7114
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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