SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 21

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
The increment generation circuit produces the Discrete Time Oscillator (DTO) increment
for both subcarrier generation blocks. It contains a division by the increment of the
line-locked clock generator to create a stable phase-locked sine signal under all conditions
(e.g. for non-standard signals).
The PAL delay line block eliminates crosstalk between the chrominance channels in
accordance with the PAL standard requirements. For NTSC color standards the delay line
can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1.
It is always disabled during VBI or raw data lines programmable by the LCRn registers
(subaddresses 41h to 57h); see
SECAM recombination (cross-over switches).
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•
Loop filter chrominance PLL (only active for PAL/NTSC standards)
PAL/SECAM sequence detection, H/2-switch generation
Rev. 03 — 17 January 2006
Section
8.2. The embedded line delay is also used for
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7114
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