SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 41

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
8.3.1.1 Input field processing
The source start offset (XO11 to XO0 and YO11 to YO0) opens the acquisition window,
and the target size (XD11 to XD0 and YD11 to YD0) closes the window, however the
window is cut vertically if there are less output lines than expected. The trigger events for
the pixel and line counts are the horizontal and vertical reference edges as defined in
subaddress 92h. The task handling is controlled by subaddress 90h; see
The trigger event for the field sequence detection from external signals (X port) are
defined in subaddress 92h. From the X port the state of the scalers H reference signal at
the time of the V reference edge is taken as field sequence identifier FID. For example, if
the falling edge of the XRV input signal is the reference and the state of XRH input is
logic 0 at that time, the detected field ID is logic 0.
The bits XFDV[92h[7]] and XFDH[92h[6]] define the detection event and state of the flag
from the X port. For the default setting of XFDV and XFDH at ‘00’ the state of the H-input
at the falling edge of the V-input is taken.
The scaler directly gets a corresponding field ID information from the SAA7114 decoder
path.
The FID flag is used to determine whether the first or second field of a frame is going to be
processed within the scaler and it is used as trigger condition for the task handling (see
bits STRC[1:0] 90h[1:0]).
According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the
application, the polarities of the detection results on the X port signals and the internal
decoder ID can be changed via XFDH.
As the V-sync from the decoder path has a half line timing (due to the interlaced video
signal), but the scaler processing only knows about full lines, during 1st fields from the
decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field.
This can be compensated for by switching the V-trigger event, as defined by XDV0, to the
opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of
the decoder can be seen in
As the H and V reference events inside the ITU 656 data stream (from X port) and the
real-time reference signals from the decoder path are processed differently, the trigger
events for the input acquisition also have to be programmed differently.
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Vertical offset defined in lines of the video source, parameter YO[11:0] 99h[3:0]
98h[7:0]
Vertical length defined in lines of the video source, parameter YS[11:0] 9Bh[3:0]
9Ah[7:0]
Vertical length defined in number of target lines, as a result of vertical scaling,
parameter YD[11:0] 9Fh[3:0] 9Eh[7:0]
Horizontal offset defined in number of pixels of the video source, parameter XO[11:0]
95h[3:0] 94h[7:0]
Horizontal length defined in number of pixels of the video source, parameter XS[11:0]
97h[3:0] 96h[7:0]
Horizontal destination size, defined in target pixels after fine scaling, parameter
XD[11:0] 9Dh[3:0] 9Ch[7:0]
Rev. 03 — 17 January 2006
Figure 24
and
Figure
25.
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7114
Section
8.3.1.2.
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