SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet
SAA7114HV2
Specifications of SAA7114HV2
Related parts for SAA7114HV2
SAA7114HV2 Summary of contents
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SAA7114 PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler Rev. 03 — 17 January 2006 1. General description The SAA7114 is a video capture device for applications at the image port of Video ...
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Philips Semiconductors 2. Features 2.1 Video decoder Six analog inputs, internal analog source selectors, e. Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters Fully programmable static gain or Automatic Gain Control (AGC) for ...
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Philips Semiconductors 2.3 VBI data decoder and slicer Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), etc. 2.4 Audio clock ...
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Philips Semiconductors 4. Quick reference data Table 1: Symbol V DDD V DDA T amb P tot(A+D) [1] 8-bit image port output mode, expansion port is 3-stated. 5. Ordering information Table 2: Type number SAA7114E SAA7114H SAA7114_3 Product data sheet ...
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XPD [ 7:0 ] LLC2 RTS0 XCLK LLC RTCO RTS1 XDQ (1) REAL-TIME OUTPUT EXPANSION PORT PIN MAPPING RES X-PORT I/O FORMATTING CE CLOCK GENERATION XTOUT AND POWER-ON CONTROL XTALI XTALO AI11 AI12 DIGITAL AI21 DECODER ANALOG WITH AI22 DUAL ...
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Philips Semiconductors 7. Pinning information 7.1 Pinning V 1 DDD(EP1) 2 TDO TDI 3 XTOUT SS(XTAL) 6 XTALO XTALI DD(XTAL SSA2 10 AI24 V 11 DDA2 AI23 12 13 AI2D AI22 14 ...
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Philips Semiconductors Fig 3. Pin configuration (LBGA156) Table 3: Pin Symbol A2 n.c. A6 n.c. A10 n.c. B1 n.c. B5 n.c. B9 n.c. B13 IPD0 C1 n.c. C5 n.c. C9 n.c. C13 IPD1 D1 n.c. D5 n.c. D9 n.c. D13 ...
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Philips Semiconductors Table 3: Pin Symbol J11 V K1 XTRI K11 V L1 XPD5 L5 XRV L9 V L13 RTCO M1 XPD2 M5 TMS M9 V M13 V N1 XPD0 N5 TDO N9 V N13 V P2 XTALI P6 AI24 ...
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Philips Semiconductors Table 4: Pin description …continued Symbol Pin LQFP100 LBGA156 DDA1 AI12 18 P11 AI1D 19 P12 AI11 20 P13 AGND 21 N10 AOUT 22 M10 V 23 N11 DDA0 V 24 N12, N13 SSA0 V ...
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Philips Semiconductors Table 4: Pin description …continued Symbol Pin LQFP100 LBGA156 IGP0 48 F14 IGP1 49 G13 V 50 H11 SSD(EP2 G11 DDD(EP3) IGPV 52 F13 IGPH 53 G12 IPD7 54 E14 IPD6 55 D14 IPD5 56 C14 ...
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Philips Semiconductors Table 4: Pin description …continued Symbol Pin LQFP100 LBGA156 TEST5 79 J2 XTRI 80 K1 XPD7 81 K2 XPD6 DDD(ICO5) XPD5 84 L1 XPD4 85 L2 XPD3 86 L3 XPD2 ...
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Table 5: 8-bit/16-bit and alternative pin function configurations [1] Pin Symbol Input 8-bit input 16-bit input modes modes (only for I programming) K2, K3 L3, XPD7 to D1 data Y data input M1, M2, N1 (81, 82, XPD0 ...
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Table 5: 8-bit/16-bit and alternative pin function configurations [1] Pin Symbol Input 8-bit input 16-bit input modes modes (only for I programming) J14 (42) ITRDY - - G12 (53) IGPH - - F13 (52) IGPV - - G13 (49) IGP1 ...
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Philips Semiconductors 8. Functional description 8.1 Decoder 8.1.1 Analog input processing The SAA7114 offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Figure 8.1.2 Analog ...
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N8 SSA1 (9) M7 SSA2 (13) P8 AI2D SOURCE (10, 12, 14, 16) SWITCH CIRCUIT P6, P7, P9, P10 AI24 to AI21 (17 DDA1 (11 DDA2 (18) P11 AI12 (19) P12 ...
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Philips Semiconductors 8.1.2.1 Clamping The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect ...
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Philips Semiconductors Fig 8. Gain flow chart SAA7114_3 Product data sheet ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 1 NO ACTION VBLK 0 510 496 1/F 1/L 1/LLC2 STOP GAIN ACCUMULATOR (18 BITS) ...
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Philips Semiconductors Fig 9. Clamp and gain flow chart SAA7114_3 Product data sheet ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK <- CLAMP 1 0 HCL 1 0 CLL NO CLAMP CLAMP CLAMP WIPE = white peak level (254). SBOT ...
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CVBS-IN or Y-IN LDEL COMPENSATION YCOMB QUADRATURE MODULATOR CVBS-IN QUADRATURE LOW-PASS 1 or CHR-IN DEMODULATOR DOWNSAMPLING SUBCARRIER GENERATION 2 CHROMINANCE INCREMENT DELAY SUBCARRIER GENERATION 1 HUEC[7:0] RTCO Fig 10. Chrominance and luminance processing Y DELAY LUMINANCE-PEAKING SUBTRACTOR OR LOW-PASS, CHR ...
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Philips Semiconductors 8.1.3.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase ...
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Philips Semiconductors • Loop filter chrominance PLL (only active for PAL/NTSC standards) • PAL/SECAM sequence detection, H/2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors 8.1.3.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered C block. Its characteristic is controlled ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors (dB (1) LCBW[2:0] = 000. 48 (2) LCBW[2:0] = 010. 51 (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. 54 ...
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Philips Semiconductors 9 V (dB (1) LUFI[3:0] = 0001. 2 (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. 1 (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = ...
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Philips Semiconductors 8.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and C following functions: • Chrominance saturation control by DSAT7 to DSAT0 • Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 ...
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Philips Semiconductors a. Sources containing 7.5 IRE black level Fig 19. CVBS (raw data) range for scaler input, data slicer and X port output 8.1.4 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further ...
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Philips Semiconductors Table 6: Clock XTALO LLC LLC2 LLC4 (internal) LLC8 (virtual) LFCO Fig 20. Block diagram of the clock generation circuit 8.1.6 Power-on reset and CE input A missing clock, insufficient digital or analog V the reset sequence; all ...
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Philips Semiconductors XTALO LLCINT RESINT LLC RES (internal reset) Fig 21. Power-on control circuit SAA7114_3 Product data sheet CLOCK PLL LLC 200 s some ms PLL delay POC = Power-on control chip enable ...
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Philips Semiconductors 8.2 Decoder output formatter The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see and the control circuit for the signals ...
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LINE NUMBER (1st FIELD) active video 259 260 261 LINE NUMBER (2nd FIELD) active video LCR LINE NUMBER (1st FIELD) 273 274 275 276 LINE NUMBER (2nd FIELD) LCR ...
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Philips Semiconductors ITU counting 622 623 310 single field counting 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID ITU counting 309 310 single field counting 310 309 CVBS HREF F_ITU656 (1) V123 VSTO [ ...
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Philips Semiconductors ITU counting 525 single field counting 262 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID ITU counting 263 262 single field counting 262 263 CVBS HREF F_ITU656 (1) V123 VSTO [ 8:0 ] ...
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Philips Semiconductors Fig 26. Horizontal timing diagram (50/60 Hz) SAA7114_3 Product data sheet CVBS input processing delay ADC to expansion port: expansion port data output HREF (50 Hz) 720 CREF 50 Hz CREF2 5 HS (50 Hz) programming range 108 ...
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Philips Semiconductors 8.3 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in previous products (e.g. SAA7140), but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to ...
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Philips Semiconductors 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via port: 16-bit data at 27 MHz clock, 1 cycle ...
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Philips Semiconductors • Vertical offset defined in lines of the video source, parameter YO[11:0] 99h[3:0] 98h[7:0] • Vertical length defined in lines of the video source, parameter YS[11:0] 9Bh[3:0] 9Ah[7:0] • Vertical length defined in number of target lines, as ...
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Philips Semiconductors Table 9: XDV1 92h[ 8.3.1.2 Task handling The task handler controls the switching between the two programming register sets controlled by subaddresses 90h and C0h. A task is enabled via the global control ...
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Philips Semiconductors • Basically the trigger conditions are checked, when a task is activated important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic ...
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Table 10: Examples for field processing Subject Field sequence frame/field [1] Example 1 Example 2 1/1 1/2 2/1 1/1 Processed by task State of detected ITU 656 FID TOGGLE fl ...
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Philips Semiconductors 8.3.2 Horizontal scaling The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: H-scale ratio H-scale ratio where the parameter of prescaler XPSC[5: ...
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Philips Semiconductors Where: • The range (value 0 is not allowed) • Npix_in = number of input pixel, and • Npix_out = number of desired output pixel over the complete horizontal scaler The use of the ...
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Philips Semiconductors Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figure 27 Table 11: PFUV[1:0] A2h[7:6] and PFY[1:0] A2h[5: (1) PFY[1:0] = ...
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Philips Semiconductors (dB 0. XC2_1 = 0; Zero’s at Fig 29. Examples for prescaler filter characteristics: effect of ...
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Philips Semiconductors Table 12: XACL[5:0] example of usage Prescale XPSC Recommended values ratio [5:0] For lower bandwidth requirements XACL[5: [ ...
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Philips Semiconductors Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAh[7:0] and XPHC[7:0] ...
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Philips Semiconductors 8.3.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh) Vertical scaling of any ratio from 64 (theoretical zoom) to The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate ...
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Philips Semiconductors 8.3.3.3 Use of the vertical phase offsets As described in interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H-sync at the falling edge of ...
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Philips Semiconductors Fig 32. Derivation of the phase related equations (example: interlace vertical scaling In Table 13 It should be noted that the equations of the unscaled case, as the geometrical reference position for all conversions is the position of ...
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Philips Semiconductors Table 13: Input field under processing Upper input lines Upper input lines Lower input lines Lower input lines Table 14: Detected input field upper lines 0 = upper lines 1 = lower lines 1 = ...
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Philips Semiconductors The supported VBI data standards are shown in For lines field, per VBI line standards can be selected (LCR24_[7:0] to LCR2_[7:0] in 57h[7:0] to 41h[7:0]: 23 The definition for line ...
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Philips Semiconductors The clock for the output interface can be derived from an internal clock, decoder, expansion port externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can MHz. ...
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Philips Semiconductors Table 16: Output format Y Y only Table 17: Name Table 18: Limit step ILLV[85h[5 8.5.2 Video FIFO (subaddress 86h) The video ...
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Philips Semiconductors 8.5.3 Text FIFO The data of the internal VBI data slicer is collected in the text FIFO before the transmission over the I port is requested (normally before the video window starts partitioned into two FIFO ...
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Philips Semiconductors As a further option possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data ...
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VBI line timing reference code ... SAV SDID DC ... EAV ANC header DID SDID DC ANC header active for DID (subaddress 5Dh) ...
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Philips Semiconductors Table 21: Bytes stream of the data slicer Nick Comment name DID, subaddress 5Dh = 00h SAV, subaddress 5Dh EAV subaddress 5Dh [ 3Eh subaddress 5Dh [ 3Fh SDID programmable via ...
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Philips Semiconductors • Audio master Clocks Nominal Increment, ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: See Table 22 Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for ...
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Philips Semiconductors Table 23: AMXCLK (MHz) 12.288 11.2896 8.192 8.6.3 Other control signals Further control signals are available to define reference clock edges and vertical references; see Table 24: Signal APLL[3Ah[3]] AMVR[3Ah[2]] LRPH[3Ah[1]] SCPH[3Ah[0]] SAA7114_3 Product data sheet Programming examples ...
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Philips Semiconductors 9. Input/output interfaces and ports The SAA7114 has 5 different I/O interfaces: • Analog video input interface, for analog CVBS and/or Y and C input signals • Audio clock port • Digital real-time signal port (RT port) • ...
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Philips Semiconductors The ratios are programmable; see Table 26: Symbol AMCLK AMXCLK J12 ASCLK ALRCLK [1] Pin numbers for LQFP100 in parenthesis. 9.3 Clock and real-time synchronization signals For the generation of the line-locked video (pixel) clock LLC, and of ...
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Philips Semiconductors Table 27: Symbol XTOUT Real-time signals (RT port) LLC LLC2 RTCO RTS0 RTS1 [1] Pin numbers for LQFP100 in parenthesis. 9.4 Video expansion port (X port) The expansion port is intended for transporting video streams image data from ...
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Philips Semiconductors Table 28: Symbol Pin XPD7 to XPD0 XCLK XDQ XRDY XRH XRV XTRI [1] Pin numbers for LQFP100 in parenthesis. 9.4.1 X port configured as output If data output is enabled at the expansion port, then the data ...
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Philips Semiconductors – Adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing This data type is defined for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. ...
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Philips Semiconductors Table 30: Bit Table 31: Line number 261 262 263 264 and 265 266 to 282 283 284 285 to 524 ...
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Philips Semiconductors Table 32: Line number 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 9.4.2 X port configured as input If the data input mode is ...
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Philips Semiconductors Available formats are as follows: • Y-C • Y-C • Raw samples • Decoded VBI data For handshake with the receiving VGA controller, or other memory or bus interface circuitry and V reference signals and programmable ...
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Philips Semiconductors There are no empty cycles in the ancillary code and its data field. The data codes 00h and FFh are suppressed (changed to 01h or FEh respectively) in the active video stream, as well as in the VBI ...
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Philips Semiconductors Table 34: Symbol Pin HPD7 to HPD0 [1] Pin numbers for LQFP100 in parenthesis. 9.7 Basic input and output timing diagrams I port and X port 9.7.1 I port output timing Figure 34 active gate signals. If reference ...
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Philips Semiconductors ICLK IDQ IPD [ 7:0 ] IGPH Fig 35. Output timing I port for serial 8-bit data at start of a line (ICODE = 0) ICLK IDQ IPD [ 7 IGPH Fig 36. ...
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Philips Semiconductors ICLK IDQ IPD [ 7 HPD [ 7 SAV IGPH Fig 38. Output timing for 16-bit data output via I port and H port with codes (ICODE = 1), timing is ...
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Philips Semiconductors 2 10. I C-bus description The SAA7114 supports the ‘fast mode’ I 400 kbit/s). 2 10.1 I C-bus format S SLAVE ADDRESS W a. Write procedure. S SLAVE ADDRESS W Sr SLAVE ADDRESS R b. Read procedure (combined). ...
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Philips Semiconductors Table 36: Subaddress 00h F0h to FFh Video decoder: 01h to 2Fh 01h to 05h 06h to 19h 1Ah to 1Eh 1Fh 20h to 2Fh Audio clock generation: 30h to 3Fh 30h to 3Ah 3Bh to 3Fh General ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Chip version: register 00h Chip version (read only) 00h Video decoder: registers 01h to 2Fh Front-end part: registers 01h to 05h Increment delay 01h Analog input control 1 02h ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Reserved 1Ah to 1Eh Status byte video decoder (read only, 1Fh OLDSB = 0) Status byte video decoder (read only, 1Fh OLDSB = 1) Reserved 20h to 2Fh Audio ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Slicer status byte 0 (read only) 60h Slicer status byte 1 (read only) 61h Slicer status byte 2 (read only) 62h Reserved 63h to 7Fh X port, I port ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Vertical input window length 9Ah 9Bh Horizontal output window length 9Ch 9Dh Vertical output window length 9Eh 9Fh FIR filtering and prescaling Horizontal prescaling A0h Accumulation length A1h Prescaler ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Vertical chrominance phase offset ‘00’ B8h Vertical chrominance phase offset ‘01’ B9h Vertical chrominance phase offset ‘10’ BAh Vertical chrominance phase offset ‘11’ BBh Vertical luminance phase offset ‘00’ ...
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Table 37: I C-bus receiver/transmitter overview Register function Subaddress D7 Luminance brightness control D4h Luminance contrast control D5h Chrominance saturation control D6h Reserved D7h Horizontal phase scaling Horizontal luminance scaling increment D8h D9h Horizontal luminance phase offset DAh Reserved ...
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Philips Semiconductors 2 10.2 I C-bus details 10.2.1 Subaddress 00h Table 38: Function Chip Version (CV) 10.2.2 Subaddress 01h The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use ...
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Philips Semiconductors Table 40: Bit D[3:0] [1] To take full advantage of the Y/C modes the I to logic 1 (full luminance bandwidth). AI24 AI23 AI22 AI21 AI12 AI11 Fig 42. Mode 0 CVBS (automatic gain) AI24 ...
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Philips Semiconductors AI24 AI23 AI22 AI21 AI12 AI11 Fig 46. Mode 4 CVBS (automatic gain) AI24 AI23 AI22 AI21 AI12 AI11 Fig 48. Mode (gain channel 2 AI24 AI23 AI22 AI21 AI12 AI11 Fig 50. Mode 8 ...
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Philips Semiconductors Table 41: Bit Description D3 automatic gain control integration D2 gain control fix D1 static gain control channel 2 sign bit D0 static gain control channel 1 sign bit [1] HLNRS = 1 should not be used in ...
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Philips Semiconductors Table 44: Delay time (step size = 8/LLC) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 10.2.8 Subaddress 07h Table 45: Delay time (step size = 8/LLC) 128... 109 (50 Hz) 128... 108 (60 Hz) 108 (50 ...
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Philips Semiconductors Table 46: Bit D[1:0] 10.2.10 Subaddress 09h Table 47: Bit SAA7114_3 Product data sheet Sync control; 08h[7:0] …continued Description Symbol vertical noise VNOI[1:0] reduction Luminance control; 09h[7:0] Description Symbol chrominance BYPS trap/comb filter bypass ...
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Philips Semiconductors Table 47: Bit D[3:0] 10.2.11 Subaddress 0Ah Table 48: Offset 255 (bright) 128 (ITU level) 0 (dark) SAA7114_3 Product data sheet Luminance control; 09h[7:0] …continued Description Symbol sharpness control, LUFI[3:0] luminance filter characteristic; see Figure 17 Luminance brightness ...
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Philips Semiconductors 10.2.12 Subaddress 0Bh Table 49: Gain 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) 1 (inverse luminance) 2 (inverse luminance) 10.2.13 Subaddress 0Ch Table 50: Gain 1.984 (maximum) 1.0 (ITU level) 0 (color off) 1 (inverse chrominance) ...
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Philips Semiconductors 10.2.15 Subaddress 0Eh Table 52: Bit D7 D[6: SAA7114_3 Product data sheet Chrominance control 1; 0Eh[7:0] Description Symbol Value clear DTO CDTO 0 1 color standard CSTD[2:0] 000 selection 001 010 011 100 101 110 ...
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Philips Semiconductors 10.2.16 Subaddress 0Fh Table 53: Bit D7 D[6:0] 10.2.17 Subaddress 10h Table 54: Bit D[7:6] D[5:4] D3 D[2:0] 10.2.18 Subaddress 11h Table 55: Bit D7 D6 D[5:4] SAA7114_3 Product data sheet Chrominance gain control; 0Fh[7:0] Description Symbol automatic ...
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Philips Semiconductors Table 55: Bit D3 D[2:0] 10.2.19 Subaddress 12h Table 56: The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]]. RTS0 output 3-state Constant LOW CREF (13.5 MHz toggling pulse; see CREF2 (6.75 MHz toggling pulse; ...
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Philips Semiconductors [1] Function selectable via HLSEL[13h[3]]: a) HLSEL = standard horizontal lock indicator. b) HLSEL = fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. ...
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Philips Semiconductors 10.2.20 Subaddress 13h Table 58: Bit D7 D6 D[5:4] D3 D[2:0] SAA7114_3 Product data sheet RT/X port output control; 13h[7:0] Description Symbol RTCO output enable RTCE X port XRH output XRHS selection X port XRV output XRVS[1:0] 00 ...
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Philips Semiconductors 10.2.21 Subaddress 14h Table 59: Analog/ADC/compatibility control; 14h[7:0] Bit Description D7 compatibility bit for SAA7199 D6 update time interval for AGC value D[5:4] analog test select D3 XTOUT output enable D2 decoder status byte selection; see Table 65 ...
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Philips Semiconductors 10.2.23 Subaddress 16h Table 61: VGATE stop; 17h[1] and 16h[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Field Frame Decimal line value counting 50 Hz 1st 1 312 2nd 314 1st 2 0... 2nd 315 ...
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Philips Semiconductors 10.2.26 Subaddress 19h Table 64: Offset 128 LSB 0 LSB +128 LSB 10.2.27 Subaddress 1Fh Table 65: Bit SAA7114_3 Product data sheet Raw data offset control; RAWO[7:0] 19h[7:0]; see Control ...
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Philips Semiconductors 10.3 Programming register audio clock generation See equations in 10.3.1 Subaddresses 30h to 32h Table 66: Subaddress 30h 31h 32h 10.3.2 Subaddresses 34h to 36h Table 67: Subaddress 34h 35h 36h 10.3.3 Subaddress 38h Table 68: Subaddress 38h ...
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Philips Semiconductors 10.4 Programming register VBI data slicer 10.4.1 Subaddress 40h Table 71: Bit Description D6 Hamming check D5 framing code error D4 amplitude searching 10.4.2 Subaddresses 41h to 57h Table 72: See Section 8.2 Name WST625 CC625 VPS WSS ...
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Philips Semiconductors 10.4.3 Subaddress 58h Table 73: According to Framing code for programmable data types Default value 10.4.4 Subaddress 59h Table 74: Horizontal offset Recommended value 10.4.5 Subaddress 5Ah Table 75: Vertical offset Minimum value 0 Maximum value 312 Value ...
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Philips Semiconductors 10.4.8 Subaddress 5Eh Table 78: Bit D[5:0] 10.4.9 Subaddress 60h Table 79: Bit Description D6 framing code valid D5 framing code valid D4 VPS valid D3 PALplus valid D2 closed caption valid 10.4.10 Subaddresses 61h and 62h Table ...
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Philips Semiconductors [ don’t care. Table 82: I port and scaler back-end clock selection ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X port ICLK output is ...
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Philips Semiconductors Table 85: I port signal definitions IGP0 is output field ID, as defined by OFIDC[90h[6]] IGP0 is A/B task flag, as defined by CONLH[90h[7]] IGP0 is sliced data flag, framing the sliced VBI data at the I port ...
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Philips Semiconductors Table 88: X port signal definitions text slicer Video data limited to range 1 to 254 Video data limited to range 8 to 247 Dword byte swap, influences serial output timing ...
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Philips Semiconductors Table 91: I port FIFO flag control and arbitration FAE FIFO flag almost empty level < 16 Dwords < 8 Dwords < 4 Dwords 0 Dwords FAF FIFO flag almost full level 16 Dwords 24 Dwords 28 Dwords ...
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Philips Semiconductors 10.5.3 Subaddress 88h Table 94: Power save control DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit ...
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Philips Semiconductors Table 96: Bit [1] Status information is unsynchronized and shows the actual status at the time of I 10.5.5 Subaddresses 90h and C0h Table 97: Event handler control Output field ID is field ID from ...
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Philips Semiconductors 10.5.6 Subaddresses 91h to 93h Table 100: X port formats and configuration; register set A [91h[7:3]] and B [C1h[7:3]] Scaler input format and configuration source selection Only if XRQT[83h[2 scaler input source reacts on SAA7114 request ...
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Philips Semiconductors Table 102: X port input reference signal definitions; register set A [92h[7:4]] and X port input reference signal definitions Rising edge of XRV input and decoder V123 is vertical reference Falling edge of XRV input and decoder V123 ...
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Philips Semiconductors Table 104: I port output format and configuration; register set A [93h[7:5]] and I port output formats and configuration Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85h bits ISWP1 and ISWP0 No ITU ...
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Philips Semiconductors 10.5.7 Subaddresses 94h to 9Bh Table 106: Horizontal input window start; register set A [94h[7:0]; 95h[3:0]] and B [C4h[7:0]; C5h[3:0]] Horizontal input acquisition window definition offset in [1] X (horizontal) direction A minimum of ‘2’ should be kept, ...
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Philips Semiconductors [1] For trigger condition: STRC[1:0] 90h[1: > (number of input lines per field conditions: YS > (number of input lines per field 10.5.8 Subaddresses 9Ch to 9Fh Table 110: Horizontal output window length; ...
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Philips Semiconductors Table 114: Prescaler DC gain and FIR prefilter control; register set A [A2h[7:4]] and FIR prefilter control Luminance FIR filter bypassed H_y(z) = H_y(z) = H_y(z) = Chrominance FIR filter bypassed H_uv(z) = H_uv(z) = H_uv(z) = [1] ...
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Philips Semiconductors 10.5.10 Subaddresses A4h to A6h Table 116: Luminance brightness control; register set A [A4h[7:0]] and B [D4h[7:0]] Luminance brightness control Value = 0 Nominal value = 128 Value = 255 Table 117: Luminance contrast control; register set A ...
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Philips Semiconductors Table 120: Horizontal luminance phase offset; register set A [AAh[7:0]] and B [DAh[7:0]] Horizontal luminance phase offset Offset = 0 Offset = Offset = Offset = Table 121: Horizontal chrominance scaling increment; register set A [ACh[7:0]; ADh[7:0]] Horizontal ...
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Philips Semiconductors Table 124: Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and Vertical chrominance scaling increment This value must be set to the luminance value YSCY[15:0] Table 125: Vertical scaling mode control; register set A [B4h[4 and 0]] ...
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Philips Semiconductors 11. Programming start setup 11.1 Decoder part The given values force the following behavior of the SAA7114 decoder part: • The analog input AI11 expects an NTSC M, PAL and I or SECAM signal ...
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Philips Semiconductors Table 128: Decoder part start setup values for the three main standards Subaddress Register function (hexadecimal) 14 analog/ADC/compatibility control 15 VGATE start, FID change 16 VGATE stop 17 miscellaneous, VGATE configuration and MSBs 18 raw data gain control ...
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Philips Semiconductors Table 129: Audio clock part setup values Subaddress Register function (hexadecimal) 37 reserved 38 clock ratio AMXCLK to ASCLK X, X, SDIV5 to SDIV0 39 clock ratio ASCLK to ALRCLK X, X, LRDIV5 to LRDIV0 3A audio clock ...
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Philips Semiconductors 11.4 Scaler and interfaces Table 131 • prsc = prescale ratio • fisc = fine scale ratio • vsc = vertical scale ratio The ratio is defined as: In the following settings the VBI data slicer is inactive. ...
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Philips Semiconductors 11.4.3 Examples Table 131: Example of configurations Example number Table 132: Scaler and interface configuration example 2 I C-bus address (hex) Global settings SAA7114_3 Product data sheet Scaler ...
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Philips Semiconductors Table 132: Scaler and interface configuration example 2 I C-bus address (hex) 88 Task A: scaler input configuration and output format settings Input and output window definition ...
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Philips Semiconductors Table 132: Scaler and interface configuration example 2 I C-bus address (hex) Vertical scaling SAA7114_3 Product data sheet Main functionality Example 1 Hex vertical scaling increment for 00 luminance 04 ...
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Philips Semiconductors 12. Limiting values Table 133: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol Parameter V DDD V DDA V ...
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Philips Semiconductors 14. Characteristics Table 135: Characteristics DDD DDA drawings and conditions illustrated in Symbol Parameter Supplies V digital supply voltage DDD I digital supply ...
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Philips Semiconductors Table 135: Characteristics …continued DDD DDA drawings and conditions illustrated in Symbol Parameter Digital inputs V LOW-level input voltage pins IL(SCL,SDA) SDA and ...
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Philips Semiconductors Table 135: Characteristics …continued DDD DDA drawings and conditions illustrated in Symbol Parameter Subcarrier PLL f nominal subcarrier frequency PAL BGHI sc(nom) f ...
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Philips Semiconductors Table 135: Characteristics …continued DDD DDA drawings and conditions illustrated in Symbol Parameter Clock output timing C output load capacitance L T cycle ...
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Philips Semiconductors clock input XCLK t SU;DAT data and control inputs (X port) input XDQ data and control outputs X port, I port clock outputs LLC, LLC2, XCLK, ICLK and ICLK input Fig 52. Data input/output timing diagram (X port, ...
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V ( DD(3.3) V DDA(3.3) L3 2.2 H 3.3 V (A) TDO TDI BST [ 2:0 ] BST2 Place 0 R24 if BST is not used 0 DGND (98) (99) ...
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Philips Semiconductors SAA7114 P2 (7) P3 (6) XTALI 32.11 MHz 4 With 3rd harmonic quartz. Crystal load = 8 pF. SAA7114 P2 (7) P3 (6) XTALI 24.576 MHz 4 ...
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Philips Semiconductors 16. Test information 16.1 Boundary scan test The SAA7114 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7114 follows the “IEEE Std. 1149.1 - Standard ...
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Philips Semiconductors When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state ...
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Philips Semiconductors 17. Package outline LBGA156: plastic low profile ball grid array package; 156 balls; body 1.05 mm ball A1 index area ...
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Philips Semiconductors LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT ...
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Philips Semiconductors 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...
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Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...
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Philips Semiconductors 19. Revision history Table 138: Revision history Document ID Release date SAA7114_3 20060117 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • Table ...
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Philips Semiconductors 20. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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Philips Semiconductors 10.2.12 Subaddress 0Bh . . . . . . . . . . . . . . . . . . . . . . . 91 10.2.13 Subaddress 0Ch . . . . . . . . ...