SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 114

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
[1]
Table 110: Horizontal output window length; register set A [9Ch[7:0]; 9Dh[3:0]] and B [CCh[7:0]; CDh[3:0]]
[1]
[2]
Table 111: Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]]
[1]
Table 112: Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]]
Table 113: Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]]
SAA7114_3
Product data sheet
Horizontal output acquisition
window definition number of
desired output pixels in
X (horizontal) direction
No output
Odd lengths are allowed, but will
be filled up to even lengths
Maximum possible number of
input pixels = 4095
Vertical output acquisition
window definition number of
desired output lines in
Y (vertical) direction
No output
1 pixel
Maximum possible number of
output lines = 4095
Horizontal integer prescaling
ratio (XPSC)
Not allowed
Downscale = 1
Downscale =
...
Downscale =
Horizontal prescaler
accumulation sequence
length (XACL)
Accumulation length = 1
Accumulation length = 2
...
Accumulation length = 64
For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field
conditions: YS > (number of input lines per field
Reference for counting are luminance samples.
If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.
If the desired output length is greater than the number of scaled output lines, the processing is cut.
1
1
10.5.8 Subaddresses 9Ch to 9Fh
10.5.9 Subaddresses A0h to A2h
2
63
[2]
[1]
[1]
Control bits
A [9Dh[3:0]] and B [CDh[3:0]] A [9Ch[7:0]] and B [CCh[7:0]]
XD11
0
0
1
Control bits
A [9Fh[3:0]] and B [CFh[3:0]] A [9Eh[7:0]] and B [CEh[7:0]]
YD11
0
0
1
Control bits D5 to D0
XPSC5
0
0
0
...
1
Control bits D5 to D0
XACL5
0
0
...
1
XD10
0
0
1
YD10
0
0
1
2), will result in field dropping.
Rev. 03 — 17 January 2006
XD9
0
0
1
YD9
0
0
1
XPSC4
0
0
0
...
1
XACL4
0
0
...
1
XD8
0
0
1
YD8
0
0
1
XPSC3
0
0
0
...
1
XACL3
0
0
...
1
XD7
0
0
1
YD7
0
0
1
XD6
0
0
1
YD6
0
0
1
XPSC2
0
0
0
...
1
XACL2
0
0
...
1
XD5
0
0
1
YD5
0
0
1
PAL/NTSC/SECAM video decoder
2), will result in field dropping. Other trigger
XD4
0
0
1
YD4
0
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
XPSC1
0
0
1
...
1
XACL1
0
0
...
1
XD3
0
0
1
YD3
0
0
1
SAA7114
XD2
0
0
1
YD2
0
0
1
XPSC0
0
1
0
...
1
XACL0
0
1
...
1
XD1
0
0
1
YD1
0
0
1
114 of 144
XD0
0
1
1
YD0
0
1
1