SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 85

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Note 2: Restrictions for frequency ratios between receive frequency (
Note 3: Restrictions for frequency ratios between receive frequency (f
1)
Semiconductor Group
Reduced to 1.5 if receive address is pushed to RFIFO in HDLC/SDLC mode.
frequency (
Normal mode; clock mode 0, 2a, and 6a:
Master clock mode:
There are no restrictions on the relative phases of the clocks. The conditions
are valid independent of strobe signals or time-slot widths: i.e. in normal mode
clock mode 1 always fulfills the condition, irrespective of how receive and
transmit data are strobed. Thus, by using strobes the above condition may
always be fulfilled irrespective of the net data rates.
frequency (f
Master clock mode:
Non bus configuration:
In addition: For a given transmit clock f
periods in the low phase of transmit clock f
Bus configuration:
In addition: For a given transmit clock f
periods in the low phase of transmit clock f
Example 1: f
(see figure 37)
Example 2: f
(see figure 38)
Generally, in master clock mode the low/high ratio of transmit clock should be
in the range 0.25/0.75 .. 0.75/0.25.
There are no restrictions on the relative phases of the clocks. The conditions
are valid independent of strobe signals or time-slot widths: i.e. in normal mode
clock mode 1 always fulfills the condition, irrespective of how receive and
transmit data are strobed. Thus, by using strobes the above condition may
always be fulfilled irrespective of the net data rates.
f
x
x
x
x
) and master clock frequency (f
) and master clock frequency (
= 2 MHz with low/high ratio of 0.25/0.75 => f
= 4 MHz with low/high ratio of 0.75/0.25 => f
85
x
x
a master clock f
a master clock f
Serial Interface (layer-1 functions)
x
x
f
m
m
has to be provided.
has to be provided.
):
):
f
f
f
f
f
r
m
r
m
m
/
/
/
/
/
f
f
x
m
f
f
f
x
x
x
SAB 82532/SAF 82532
3
3
2.5;
2.5
5
1)
1)
m
m
m
m
with at least 1.25 f
f
r
with at least 2.5 f
/
= 20 MHz
= 13.32 MHz
f
m
3
f
r
r
1)
), transmit
), transmit
.
07.96
m
m