SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 79

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

7.4
7.4.1
If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted
with a selectable number of repetitions after Interframe Timefill transmission is stopped
and a new frame is ready to be sent out.
Note: If the preamble pattern equals the SYN pattern, reception is triggered by the
7.4.2
If data transfer from system memory to the ESCC2 is done by DMA (DMA bit in XBCH
set), the number of characters to be transmitted is usually defined via the Transmit Byte
Count registers (XBCH, XBCL: bits XBC11 … XBC0).
Setting the ‘Transmit Continuously’ (XC) bit in XBCH, however, the byte count value is
ignored and the DMA interface of ESCC2 will continuously request for transmit data any
time 32 new characters can be entered in XFIFO.
This feature can be used to transmit frames of length higher than the byte count specified
by XBCH, XBCL (frames with more than 4095 bytes).
Note: If the XC bit is reset during continuous transmission, the transmit byte count
7.4.3
If the internal CRC generator is not used for calculation of Frame Check Sequence, an
externally calculated checksum (16 bits) can be appended to the message frame without
internally generated parity information, although parity is enabled for data characters.
Prerequisites are:
• CRC generator disabled (CAPP = ‘0’),
• CON = ‘0’ for all data characters which are to be included into parity generation
• CON = ‘1’ for both bytes defining the CRC checksum,
• Message End indication has to be issued after the checksum is written to XFIFO.
The programmed character length has no influence on this function.
Semiconductor Group
(normal operation),
preamble.
becomes valid again, and the ESCC2 will request the amount of DMA transfers
programmed via XBC11 … XBC0. Otherwise, the continuous transmission and
the generation of DMA input requests is stopped when a data underrun condition
occurs in XFIFO. Instead of CRC, continuous ‘1’s (IDLE) are transmitted
thereafter.
Special Functions
Preamble Transmission
Continuous Transmission (DMA mode only)
CRC Parity Inhibit
Character Oriented Serial Mode (MONOSYNC/BISYNC)
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SAB 82532/SAF 82532
07.96