SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 12

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
1.3
P-LCC-68
11
12
13
Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-80
43
44
45
Symbol
RD/DS
WR/R/W
CS
Input (I)
Output (O)
I
I
I
12
Function
Read Enable
(Siemens/Intel bus mode)
This signal indicates a read operation.
When the ESCC2 is selected via CS the
READ signal enables the bus drivers to
output data from an internal register
addressed via A0 … A6 on to Data Bus.
For more information about control/status
register and FIFO access in the different
bus interface modes refer to chapter 2.
If DMA transfer is selected via DACKA or
DACKB, the RD signal enables the bus
drivers to put data from the corresponding
Receive FIFO on the Data Bus. Inputs
A1 … A6 are ignored. A0 and BHE/BLE
are used to select byte or word access.
Data Strobe (Motorola bus mode)
This pin serves as input to control
read/write operations.
Write Enable
(Siemens/Intel bus mode)
This signal indicates a write operation.
When CS is active the ESCC2 loads an
internal register with data provided via the
Data Bus. For more information about
control/status register and FIFO access in
the different bus interface modes refer to
chapter 2.
If DMA transfer is selected via DACKA or
DACKB, the WR signal enables latching
data from the Data Bus on the top of the
corresponding Transmit FIFO. Inputs
A0 … A6 are ignored.
Read/Write Enable (Motorola bus mode)
This signal distinguishes between read
and write operation.
Chip Select
A low signal selects the ESCC2 for
read/write operations. CS has no function
in interrupt acknowledge or DMA cycles.
SAB 82532/SAF 82532
Introduction
07.96