SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 64

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
5.4
5.4.1
The closing flag of a previously transmitted frame simultaneously becomes the opening
flag of the following frame if there is one to be transmitted. The ‘Shared Flag’ feature is
enabled by setting bit SFLG in control register CCR1.
5.4.2
If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted
with a selectable number of repetitions after Interframe Timefill transmission is stopped
and a new frame is ready to be sent out.
Note: Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
5.4.3
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via register CCR2. In this case the Frame Check Sequence consists of four
bytes.
5.4.4
When programmed in the extended transparent mode via the MODE register
(MODE:MDS1, MDS0 = ‘11’), each channel of the ESCC2 performs fully transparent
data transmission and reception without HDLC framing, i.e. without
• FLAG insertion and deletion
• CRC generation and checking
• bit stuffing.
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and
FF
Data transmission is always performed out of XFIFO by directly shifting the contents of
XFIFO via the serial transmit data pin (TxD). Transmission is initiated by setting
CMDR:XTF (08
In receive direction, the character last assembled via receive data line (RxD) is available
in RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1, MDS0,
ADM = ‘111’), received data is shifted into RFIFO.
H
has to be written to XAD1, XAD2 and RAH2.
function the programmed preamble value should be different from Receive
Address Byte values defined for any of the connected stations.
Special Functions
Shared Flags
Preamble Transmission
CRC-32
Extended Transparent Transmission and Reception
H
); end of transmission is indicated by ISR1:EXE (10
64
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
H
).
07.96