SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 136

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

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Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Semiconductor Group
ODS …
ITF/OIN …
CM2 … CMO …
Output Driver Select
Defines the function of the transmit data pin (TxD)
0 … TxD pin is an open drain output.
1 … TxD pin is a push-pull output.
Note: This feature is also valid for pin RxD if it is switched to
Interframe Time-Fill / One Insertion
The function of this bit depends on the selected Serial Port
Configuration (bit SC1):
• Point-to-point configurations: ITF
• 0 … Continuous logical ‘1’ is output
• Bus configurations: OIN
Note: In bus configurations, the ITF is implicitly set to ‘0’, i.e.
Clock Mode
Selects one of 8 different clock modes:
000
.
.
.
111
Determines the idle (= no data to send) state of the transmit
data pin TxD
1 … Continuous FLAG sequences are output (‘01111110’-bit
When this bit is set, a ‘ONE’ insertion (deletion) mechanism is
activated: a ‘1’ is inserted after seven consecutive ‘0’s in the
transmit data stream and a ‘1’ is deleted after seven
consecutive ‘0’ in the receive data stream.
Similar to the HDLC bit stuffing mechanism (inserting a ‘0’ after
five consecutive ‘1’s), this enables clock information to be
recovered from the receive data stream by means of a DPLL
even in the case of NRZ encoding, because a transition at bit
cell boundary occurs at least every 7 bits. The ‘One Insertion’
cannot be used in conjunction with the master clock option.
TxD function via bit CCR2:SOC1.
continuous ‘1’s are transmitted, and data encoding is NRZ.
.
.
.
clock mode 0
clock mode 7
patterns)
136
Detailed Register Description
SAB 82532/SAF 82532
HDLC Mode
07.96

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