SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 169

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

FLON …
RAC …
RTS …
TRS …
TLP …
Semiconductor Group
Flow Control ON
The in-band flow control is activated via this bit:
0 … No further action is automatically taken by the ESCC2.
1 … The reception of an XOFF character (defined via register
Receiver Active
Switches the receiver to operational or inoperational state.
0 … receiver inactive
1 … receiver active
Request To Send
Defines the state and control of RTS pin.
0 … The RTS pin is controlled by the ESCC2 autonomously. RTS
1 … The RTS pin is controlled by the CPU. If this bit is set, the
Timer Resolution
Selects the resolution of the internal timer (factor k, see
description of TIMR register):
0 … k = 32 768
1 … k = 512
Test Loop
Input and output of the ASYNC channels are internally connected.
(transmitter channel A – receiver channel A/
transmitter channel B – receiver channel B).
However, recognition of an XON or an XOFF character
(defined via registers XON and XOFF) causes always a
corresponding maskable interrupt status to be generated
(refer to register ISR1).
XOFF) automatically turns off the transmitter after the
currently transmitted character (if any) has been completely
shifted out (XOFF state). The reception of an XON character
(defined via register XON) automatically makes the
transmitter resume transmitting (XON state).
is activated when data transmission starts and deactivated
when transmission is completed.
RTS pin is activated immediately and remains active till this
bit is reset.
169
Detailed Register Description
SAB 82532/SAF 82532
ASYNC Mode
07.96