SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 231
SAF82532N10V32A
Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet
1.SAB82532H10V32A.pdf
(272 pages)
Specifications of SAF82532N10V32A
Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN
SAF82532N10V32AIN
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Manufacturer
Quantity
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Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
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RFO …
RPF …
Interrupt Status Register 1 (ISR1)
Access: read
Value after RESET: 00
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC:VIS is set ‘1’, interrupt statuses in ISR1 may be flagged although they are
ALLS …
XDU …
Semiconductor Group
ISR1
masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
7
0
Receive FIFO Overflow
This interrupt is generated if RFIFO is full and a further character
is received. This interrupt can be used for statistical purposes and
indicates that the CPU does not respond quickly enough to an
RPF or TCD interrupt.
Receive Pool Full
This bit is set if RFIFO is filled with data (character and optional
status information) up to the programmed threshold level.
Note: This interrupt is only generated in Interrupt Mode.
All Sent
This bit is set when the XFIFO is empty and the last character is
completely sent out on TxD.
Transmit Data Underrun
A block of data in transmission has been terminated with IDLE,
because the XFIFO contains no further data.
Note: Transmitter and XFIFO are reset and deactivated if this
H
condition occurs. They are reactivated not before this
interrupt status register has been read. Thus, XDU should
not be masked via register IMR1.
0
address: ch-A: 3B
ALLS
ch-B: 7B
231
XDU
H
H
TIN
Detailed Register Description
SAB 82532/SAF 82532
CSC
XMR
BISYNC Mode
XPR
07.96
0
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