ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 9

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4
To complete the Ethernet interface, the ENC28J60
requires several standard components to be installed
externally. These components should be connected as
shown in Figure 2-4.
The internal analog circuitry in the PHY module requires
that an external 2.32 kΩ, 1% resistor be attached from
RBIAS to ground. The resistor influences the TPOUT+/-
signal amplitude. The resistor should be placed as close
as possible to the chip with no immediately adjacent
signal traces to prevent noise capacitively coupling into
the pin and affecting the transmit behavior. It is
recommended that the resistor be a surface mount type.
Some of the device’s digital logic operates at a nominal
2.5V. An on-chip voltage regulator is incorporated to
generate this voltage. The only external component
required is an external filter capacitor, connected from
V
lent series resistance (ESR), with a typical value of
10 μF, and a minimum value of 1 μF. The internal
regulator is not designed to drive external loads.
On the TPIN+/TPIN- and TPOUT+/TPOUT- pins,
1:1 center taped pulse transformers, rated for Ethernet
operations, are required. When the Ethernet module is
enabled, current is continually sunk through both
TPOUT pins. When the PHY is actively transmitting, a
differential voltage is created on the Ethernet cable by
varying the relative current sunk by TPOUT+ compared
to TPOUT-.
FIGURE 2-4:
© 2008 Microchip Technology Inc.
CAP
Note 1:
to ground. The capacitor must have low equiva-
MCU
Magnetics, Termination and Other
External Components
2:
3:
I/O
SCK
SDO
SDI
INT0
Ferrite Bead should be rated for at least 80 mA.
Required only if the microcontroller is operating at 5V. See Section 2.5 “I/O Levels” for more information.
These components are installed for EMI reduction purposes.
ENC28J60 ETHERNET TERMINATION AND EXTERNAL CONNECTIONS
Logic
Level
Shift
(2)
10 μF
CS
SCK
SI
SO
INT
V
CAP
ENC28J60
LEDA
TPOUT
TPOUT
Preliminary
RBIAS
TPIN
TPIN
LEDB
+
+
-
-
49.9Ω, 1%
49.9Ω, 1%
49.9Ω, 1%
49.9Ω, 1%
A common-mode choke on the TPOUT interface, placed
between the TPOUT pins and the Ethernet transformer
(not shown), is not recommended. If a common-mode
choke is used to reduce EMI emissions, it should be
placed between the Ethernet transformer and pins 1 and
2 of the RJ-45 connector. Many Ethernet transformer
modules include common-mode chokes inside the same
device package. The transformers should have at least
the isolation rating specified in Table 16-5 to protect
against static voltages and meet IEEE 802.3 isolation
requirements (see Section 16.0 “Electrical Character-
istics” for specific transformer requirements). Both
transmit and receive interfaces additionally require two
resistors and a capacitor to properly terminate the
transmission line, minimizing signal reflections.
All power supply pins must be externally connected to
the same power source. Similarly, all ground refer-
ences must be externally connected to the same
ground node. Each V
a 0.1 μF ceramic bypass capacitor (not shown in the
schematic) placed as close to the pins as possible.
Since relatively high currents are necessary to operate
the twisted-pair interface, all wires should be kept as
short as possible. Reasonable wire widths should be
used on power wires to reduce resistive loss. If the
differential data lines cannot be kept short, they should
be routed in such a way as to have a 100Ω characteristic
impedance.
2.32 kΩ, 1%
3.3V
Ferrite
Bead
0.1 μF
0.1 μF
(1,3)
(3)
1:1 CT
1:1 CT
75Ω
DD
(3)
and V
75Ω
ENC28J60
(3)
SS
75Ω
pin pair should have
(3)
1 nF, 2 kV
75Ω
DS39662C-page 7
(3)
1
(3)
RJ-45
1
2
3
4
5
6
7
8