ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 38

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENC28J60
REGISTER 6-3:
REGISTER 6-4:
DS39662C-page 36
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
DEFER: Defer Transmission Enable bit (applies to half duplex only)
1 = When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting
0 = When the medium is occupied, the MAC will abort the transmission after the excessive deferral
BPEN: No Backoff During Backpressure Enable bit (applies to half duplex only)
1 = After incidentally causing a collision during backpressure, the MAC will immediately begin
0 = After incidentally causing a collision during backpressure, the MAC will delay using the Binary
NOBKOFF: No Backoff Enable bit (applies to half duplex only)
1 = After any collision, the MAC will immediately begin retransmitting
0 = After any collision, the MAC will delay using the Binary Exponential Backoff algorithm before
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
BBIPG6:BBIPG0: Back-to-Back Inter-Packet Gap Delay Time bits
When FULDPX (MACON3<0>) = 1:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 9.6 μs.
When FULDPX (MACON3<0>) = 0:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 9.6 μs.
BBIPG6
DEFER
R/W-0
R/W-0
to transmit (use this setting for IEEE 802.3™ compliance)
limit is reached
retransmitting
Exponential Backoff algorithm before attempting to retransmit (normal operation)
attempting to retransmit (normal operation)
MACON4: MAC CONTROL REGISTER 4
MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
BBIPG5
R/W-0
R/W-0
BPEN
NOBKOFF
BBIPG4
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BBIPG3
R/W-0
U-0
—
BBIPG2
R/W-0
U-0
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
BBIPG1
R/W-0
R-0
r
BBIPG0
R/W-0
R-0
r
bit 0
bit 0