ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 65

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.0
The ENC28J60 has multiple interrupt sources and an
interrupt output pin to signal the occurrence of events
to the host controller. The interrupt pin is designed for
use by a host controller that is capable of detecting
falling edges.
Interrupts are managed with two registers. The EIE
register contains the individual interrupt enable bits for
each interrupt source, while the EIR register contains
the corresponding interrupt flag bits. When an interrupt
occurs, the interrupt flag is set. If the interrupt is
enabled in the EIE register and the INTIE global inter-
rupt enable bit is set, the INT pin will be driven low (see
Figure 12-1).
FIGURE 12-1:
© 2008 Microchip Technology Inc.
Note:
INTERRUPTS
PLNKIF
PLNKIE
interrupt flag bits are set when an interrupt
Except for the LINKIF interrupt flag,
condition occurs regardless of the state of
its corresponding enable bit or the associ-
ated global enable bit. User software
should ensure the appropriate interrupt flag
bits are clear prior to enabling an interrupt.
This feature allows for software polling.
ENC28J60 INTERRUPT LOGIC
PGEIE
PGIF
LINKIF
RXERIE
RXERIF
TXERIE
TXERIF
DMAIE
LINKIE
DMAIF
PKTIF
PKTIE
TXIE
TXIF
Preliminary
When an enabled interrupt occurs, the interrupt pin will
remain low until all flags which are causing the interrupt
are cleared or masked off (enable bit is cleared) by the
host controller. If more than one interrupt source is
enabled, the host controller must poll each flag in the
EIR register to determine the source(s) of the interrupt.
It is recommended that the Bit Field Clear (BFC) SPI
command be used to reset the flag bits in the EIR reg-
ister rather than the normal Write Control Register
(WCR) command. This is necessary to prevent
unintentionally altering a flag that changes during the
write command. The BFC and WCR commands are
discussed in detail in Section 4.0 “Serial Peripheral
Interface (SPI)”.
After an interrupt occurs, the host controller should
clear the global enable bit for the interrupt pin before
servicing the interrupt. Clearing the enable bit will
cause the interrupt pin to return to the non-asserted
state (high). Doing so will prevent the host controller
from missing a falling edge should another interrupt
occur while the immediate interrupt is being serviced.
After the interrupt has been serviced, the global enable
bit may be restored. If an interrupt event occurred while
the previous interrupt was being processed, the act of
resetting the global enable bit will cause a new falling
edge on the interrupt pin to occur.
INTIE
INT
ENC28J60
DS39662C-page 63
INT