ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 53

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1
The Unicast receive filter checks the destination
address of all incoming packets. If the destination
address exactly matches the contents of the MAADR
registers, the packet will meet the Unicast filter criteria.
8.2
The Pattern Match filter selects up to 64 bytes from the
incoming packet and calculates an IP checksum of the
bytes. The checksum is then compared to the EPMCS
registers. The packet meets the Pattern Match filter
criteria if the calculated checksum matches the EPMCS
registers. The Pattern Match filter may be useful for
filtering packets which have expected data inside them.
To use the Pattern Match filter, the host controller must
program the Pattern Match offset (EPMOH:EPMOL),
all of the Pattern Match mask bytes (EPMM7:EPMM0)
and the Pattern Match Checksum register pair
(EPMCSH:EPMCSL). The Pattern Match offset should
be loaded with the offset from the beginning of the des-
tination address field to the 64-byte window which will
be used for the checksum computation. Within the
64-byte window, each individual byte can be selectively
included or excluded from the checksum computation
by setting or clearing the respective bit in the Pattern
Match mask. If a packet is received which would cause
the 64-byte window to extend past the end of the CRC,
FIGURE 8-3:
© 2008 Microchip Technology Inc.
Note:
Input Configuration:
EMPOH:EPMOL = 0006h
EPMM7:EPMM0 = 0000000000001F0Ah
EPMCSH:EPMCSL = 563Fh
Received
Data
Byte #
Bytes used for
Checksum Computation
Values Used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h}
(00h padding byte added by hardware)
Field
Unicast Filter
Pattern Match Filter
Received data is shown in hexadecimal. Byte numbers are shown in decimal format.
11 22 33 44 55 66 77 88 99 AA BB CC 00 5A
0 1 2 3 4 5
SAMPLE PATTERN MATCH FORMAT
DA
6 7 8 9 10 11
SA
Preliminary
Type/Length
64-Byte Window Used
for Pattern Match
12 13
the filter criteria will immediately not be met, even if the
corresponding mask bits are all ‘0’. The Pattern Match
Checksum registers should be programmed to the
checksum which is expected for the selected bytes.
The checksum is calculated in the same manner that
the
Section 13.2 “Checksum Calculations”). Data bytes
which have corresponding mask bits programmed to ‘0’
are completely removed for purposes of calculating the
checksum, as opposed to treating the data bytes as
zero.
As an example, if the application wished to filter all
packets having a particular source MAC address of
00-04-A3-FF-FF-FF, it could program the Pattern
Match offset to 0000h and then set bits 6 and 7 of
EPMM0 and bits 0, 1, 2 and 3 of EPMM1 (assuming all
other mask bits are ‘0’). The proper checksum to pro-
gram into the EPMCS registers would be 0x5BFC. As
an alternative configuration, it could program the offset
to 0006h and set bits 0, 1, 2, 3, 4 and 5 of EPMM0. The
checksum would still be 5BFCh. However, the second
case would be less desirable as packets less than
70 bytes long could never meet the Pattern Match
criteria, even if they would generate the proper
checksum given the mask configuration.
Another example of a Pattern Matching filter is
illustrated in Figure 8-3.
DMA
09 0A 0B 0C 0D . . . 40 . . . FE 45 23 01
14 15 16 17 18 . . . 70 . . .
module
Data
calculates
ENC28J60
checksums
DS39662C-page 51
FCS
(see