ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 75

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.0
The ENC28J60 may be commanded to power-down
via the SPI interface. When powered down, it will no
longer be able to transmit and receive any packets.
To maximize power savings:
1.
2.
3.
4.
5.
In Sleep mode, all registers and buffer memory will
maintain their states. The ETH registers and buffer
memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see
Section 2.3 “CLKOUT Pin”).
TABLE 14-1:
© 2008 Microchip Technology Inc.
ESTAT
ECON2
ECON1
Legend: — = unimplemented, read as ‘0’, r = reserved bit. Shaded cells are not used for power-down.
Note 1:
Name
Turn
ECON1.RXEN.
Wait for any in-progress packets to finish being
received by polling ESTAT.RXBUSY. This bit
should be clear before proceeding.
Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
Set ECON2.VRPS (if not already set).
Enter Sleep by setting ECON2.PWRSV. All
MAC,
inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
POWER-DOWN
CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
off
MII
AUTOINC PKTDEC
TXRST
packet
Bit 7
SUMMARY OF REGISTERS USED WITH POWER-DOWN
INT
and
PHY
reception
BUFER
RXRST
Bit 6
registers
by
PWRSV
DMAST
Bit 5
r
become
clearing
LATECOL
CSUMEN TXRTS
Preliminary
Bit 4
r
VRPS
When normal operation is desired, the host controller
must perform a slightly modified procedure:
1.
2.
3.
After leaving Sleep mode, there is a delay of many
milliseconds before a new link is established (assuming
an appropriate link partner is present). The host
controller may wish to wait until the link is established
before attempting to transmit any packets. The link
status
PHSTAT2.LSTAT bit. Alternatively, the link change
interrupt may be used if it is enabled. See
Section 12.1.5
(LINKIF)” for additional details.
Bit 3
—
Wake-up by clearing ECON2.PWRSV.
Wait at least 300 μs for the PHY to stabilize. To
accomplish the delay, the host controller may
poll ESTAT.CLKRDY and wait for it to become
set.
Restore
ECON1.RXEN.
RXBUSY
can
RXEN
Bit 2
—
receive
be
“Link
TXABRT CLKRDY
determined
BSEL1
Bit 1
—
Change
capability
ENC28J60
BSEL0
Bit 0
by
—
DS39662C-page 73
Interrupt
by
(1)
polling
on page
setting
Values
Reset
13
13
13
Flag
the