EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 267

IC STRATIX GX FPGA 25KLE 672FBGA

EP1SGX25CF672C7

Manufacturer Part Number
EP1SGX25CF672C7
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX25CF672C7

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
4.38597GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25CF672C7
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA
0
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA
Quantity:
460
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1SGX25CF672C7ES
Manufacturer:
ALTERA
0
Part Number:
EP1SGX25CF672C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1SGX25CF672C7N
Manufacturer:
ALTERA
0
Altera Corporation
June 2006
t
f
f
t
t
t
t
t
t
t
f
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3)
Symbol
External feedback clock compensation
time
Output frequency for internal global or
regional clock
Output frequency for external clock
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays)
Time required to lock from end of
device configuration
PLL internal VCO operating range
(3)
Parameter
(4)
(10)
(6) (10)
(2)
(5)
Min
300
0.3
0.3
(8)
45
10
Typ
Stratix GX Device Handbook, Volume 1
±20 mUI for <200 MHz outclk
±100 ps for >200 MHz outclk
DC & Switching Characteristics
289/f
193/f
600
Max
420
434
100
400
55
SCANCLK
SCANCLK
22
6
(7)
ps or
MHz
MHz
MHz
MHz
Unit
mUI
6–65
ns
μs
μs
%

Related parts for EP1SGX25CF672C7