EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 264

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

High-Speed I/O Specification
6–62
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
Output t
t
t
f
f
f
t
t
t
f
f
DUTY
LOCK
IN
INDUTY
EINDUTY
INJITTER
EINJITTER
FCOMP
OUT
OUT_EXT
Table 6–87. High-Speed I/O Specifications (Part 4 of 4)
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)
Symbol
Symbol
When J = 4, 7, 8, and 10, the SERDES block is used.
When J = 2 or J = 1, the SERDES is bypassed.
Number of parallel CLK cycles.
Number of repetitions.
FALL
Table
Input clock frequency
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time
Output frequency for internal global or
regional clock
Output frequency for external clock
6–87:
LVDS
HyperTransport
technology
LVPECL
PCML
LVDS (J = 2 through
10)
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
All
(3)
Conditions
Parameter
PLL Timing
Tables 6–88
specifications.
through
47.5
Min
110
105
-5 Speed Grade
80
90
45
(2)
110
170
130
140
Typ
50
50
6–90
3
Min Typ
0.3
0.3
40
40
Max
52.5
120
200
160
175
100
(1)
55
describe the Stratix GX device enhanced PLL
Notes
47.5
Min
110
105
-6 Speed Grade
80
90
45
(1),
110
170
130
140
Typ Max
50
50
(2)
52.5
120
200
160
175
100
55
±200
±200
Max
684
500
526
60
60
6
47.5
Min
110
100
110
-7 Speed Grade
80
45
(2)
(2)
Altera Corporation
Typ Max
110
170
135
145
50
50
52.5
120
200
160
175
100
55
June 2006
MHz
MHz
MHz
Unit
Unit
ps
ps
ns
%
%
ps
ps
ps
ps
μs
%
%