EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 230

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Timing Model
6–28
Stratix GX Device Handbook, Volume 1
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M4KRC
M4KWC
M4KWERESU
M4KWEREH
M4KBESU
M4KBEH
M4KDATAASU
M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
M R A M R C
MRAMWC
MRAMWERESU
MRAMWEREH
MRAMBESU
MRAMBEH
MRAMDATAASU
MRAMDATAAH
MRAMADDRASU
MRAMADDRAH
Table 6–40. M4K Block Internal Timing Microparameter Descriptions
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Symbol
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
Parameter
Parameter
Altera Corporation
June 2006