ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 4

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
DETAILED LIST OF SILICON ANOMALIES
The following list details all known silicon anomalies for the ADSP-BF531/BF532/BF533 including a description, workaround, and
identification of applicable silicon revisions.
1.
05000074 - Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported:
DESCRIPTION:
A multi-issue instruction with dsp32shiftimm in slot 1 and a P register store in slot 2 is not supported. It will cause an exception.
The following type of instruction is not supported because the P3 register is being stored in slot 2 with a dsp32shiftimm in slot 1:
Examples of supported instructions:
WORKAROUND:
In assembly programs, separate the multi-issue instruction into 2 separate instructions. The VisualDSP++ runtime libraries do not use the
unsupported instructions. Additionally, the VisualDSP++ Blackfin compiler does not generate the unsupported instructions when
targeting the parts and silicon revisions affected by this anomaly
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
R0 = R0 << 0x1 || [ P0 ] = P3 || NOP;
R0 = R0 << 0x1 || [ P0 ] = R1 || NOP;
R0 = R0 << 0x1 || R1 = [ P0 ] || NOP;
R0 = R0 << 0x1 || P3 = [ P0 ] || NOP;
NR003532D | Page 4 of 45 | July 2008
//Not Supported - Exception
Silicon Anomaly List