ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 26

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
46.
47.
DESCRIPTION:
A committed pending write into the sub-bank targeted by the first of two consecutive dual-DAG operations will be lost when:
1) Data cache is enabled, AND
2) For the first dual-DAG access, DAG0 is a cache miss, DAG1 is a read, and both accesses alias to the same non-L1 sub-bank, AND
3) The second dual-DAG is the next instruction, and DAG1 is an access (read or write) of L1 SRAM, AND
4) There's an unpredicted change of flow within three clock cycles after the first dual-DAG access. The user has no control over the change
of flow.
WORKAROUND:
1) Don't use data cache, OR
2) Avoid consecutive dual-DAG memory accesses where the first dual-DAG access:
a) has both DAGs targeting L2, AND
b) has both DAGs aliasing to the same sub-bank, AND
c) includes a read by DAG1, which is then immediately followed by the second dual-DAG access where DAG1 is an L1 access.
The VisualDSP++ Blackfin Compiler includes a workaround for this anomaly. The compiler will automatically enable the workaround for
the appropriate silicon revisions and part numbers, or you can enable the workaround manually by specifying the compiler flag ‘-
workaround stores-to-data-cache-262'.
With the workaround enabled the compiler will ensure that dual dag instructions which may trigger the anomaly are not issued. The
compiler will attempt to use any bank information available to determine cases where the workaround is not required.
The macro __WORKAROUND_LOST_STORES_TO_DATA_CACHE_262 will be defined at compile, assemble and link build phases when the
workaround is enabled.
The VisualDSP++ runtime libraries have been built and modified, where appropriate, to avoid the anomaly.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
There is an error in the hardware loop logic which can cause incorrect instructions to get executed when the processor is running loops
and instruction ICPLB exceptions occur.
WORKAROUND:
Either:
1) Avoid using hardware loops, OR
2) Make sure hardware loops are located only in L1 memory, OR
3) Make sure ICPLB exceptions do not occur while executing a hardware loop located outside L1 memory.
If a hardware loop is contained within L1 memory, the loop must not generate an ICPLB exception, for example, by crossing a CPLB page
boundary into a page with no valid CPLB definitions. In addition, do not allow branching out to non-L1 memory from within the loop
when an ICPLB exception might be generated at the target address. Also, if the loop might be interrupted and the interrupt service
routines (ISR) reside in non-L1 memory, the ISRs should not generate ICPLB exceptions.
APPLIES TO REVISION(S):
0.3, 0.4
05000262 - Stores To Data Cache May Be Lost:
05000263 - Hardware Loop Corrupted When Taking an ICPLB Exception:
NR003532D | Page 26 of 45 | July 2008
Silicon Anomaly List