ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 37

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
65.
66.
DESCRIPTION:
The ALT_TIMING bit (bit 8) of the PPI_CONTROL register, which allows software to configure which edge the PPI data is sampled on with
respect to the PPI frame sync, is not functional. The bit always reads as 0, and writing a 1 has no effect.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
Fetches at the boundary of either reserved memory or L1 Instruction cache memory (if instruction cache enabled) which is covered by a
valid CPLB cause a false Hardware Error (External Memory Addressing Error).
WORKAROUND:
1) Do not place branch instructions or data at page boundaries. Leave at least 76 bytes free before any boundary with a reserved memory
space. This will prevent false exceptions from occuring.
2) Have the exception handler confirm whether the exception was valid or not before taking action. This can be done by verifying if the
CODE_FAULT_ADDR (or the DATA_FAULT_ADDR) register contains an address that is within a valid page. In that case, no action is
performed.
Note that this anomaly also happens on the boundary of L1_code_cache if instruction cache is enabled.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000306 - ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional:
05000310 - False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory:
NR003532D | Page 37 of 45 | July 2008
ADSP-BF531/BF532/BF533