ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
35.
DESCRIPTION:
When instruction cache is enabled, a CSYNC/SSYNC/IDLE around a Change of Control (including asynchronous exceptions/interrupts) can
cause unpredictable results.
An example of the most common sequence that can cause this issue consists of a BRCC (NP) followed by CSYNC/SSYNC/IDLE anywhere in
the next three instructions. An example is:
Another sequence that would encounter this problem would be if a BRCC (BP) which points to a CSYNC/SSYNC/IDLE is followed by a
stalling instruction that allows the speculatively fetched CSYNC/SYNC/IDLE to "catch up" to the BRCC to within two cycles:
This sequence is extremely difficult to reproduce with a failure. It requires an exact combination of stalls before the BRCC along with
some very specific cache behavior.
WORKAROUND:
Turning the instruction cache off is one way to avoid the anomaly.
If you are programming in assembly, avoid the scenario described above. The Blackfin assembler will warn users who write assembly
code that can potentially trigger the anomaly. Warning ea5507 will be issued by the assembler when a CSYNC or SSYNC could possibly be
affected by the hardware anomaly.
The VisualDSP++ Blackfin compiler includes a workaround for this hardware anomaly for all cases not related to asynchronous events. The
compiler will automatically enable the workaround for the appropriate silicon revisions and part numbers, or you can enable the
workaround manually by specifying the compiler flag -workaround speculative-syncs. With the workaround enabled, the compiler will
insert nops to avoid the anomaly condition. The following forms of the anomaly are avoided by the compiler:
The macro __WORKAROUND_SPECULATIVE_SYNCS will be defined at compile, assemble, and link build phases when the workaround is
enabled. The VisualDSP++ run-time libraries also avoid this anomaly for appropriate silicon revisions and part numbers.
For asynchronous interrupt events, the SSYNC/CSYNC/IDLE instruction can be protected by disabling interrupts and padding the
SSYNC/CSYNC/IDLE with 2 leading NOPs:
For exceptions, 3 padding NOPs should be implemented following any access to a cacheable region of memory.
Finally, as the workaround involves Supervisor Mode instructions to disable and enable interrupts, this does not apply to User Mode. In
user space, do not use CSYNC or SSYNC instructions.
05000244 - If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures:
BRCC X [predicted not taken]
nop
nop
CSYNC/SSYNC/IDLE
BRCC X (bp)
Y: ...
X: CSYNC/SSYNC/IDLE
IF CC JUMP ...;
CSYNC/SSYNC/IDLE
CSYNC/SSYNC/IDLE
CSYNC/SSYNC/IDLE
CLI R0;
NOP;
NOP;
CSYNC/SSYNC/IDLE
STI R0;
...
// this instruction is bad in any of the 3 instructions following BRCC X
NR003532D | Page 19 of 45 | July 2008
IF CC JUMP X (BP);
...
...
X: CSYNC/SSYNC/IDLE
ADSP-BF531/BF532/BF533
LSETUP(LT, LB)
X: ...
LT: CSYNC/SSYNC/IDLE
LB: NOP;
CSYNC/SSYNC/IDLE
IF CC JUMP X: