ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 33

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
58.
59.
DESCRIPTION:
In some instances, exiting an interrupt service routine (ISR) without restoring context may be desired. Consider the following sequence:
This sequence will return from the current interrupt level and then immediately execute the level 14 interrupt service routine. Ideally, the
latter would then restore the context before returning to user level, thus saving time in the first ISR.
In order to describe the problem, assume that the first interrupt occurs at an instruction like:
or any similar instruction.
The processor will jump to the ISR (RETI will contain the address of instruction C). If the ISR changes Py, when the processor reaches
instruction B above, it will speculatively fetch instruction C, which could now point to an invalid address. Because of instruction A,
instruction B will not be executed, however, the hardware error condition will be latched. The hardware exception will then be triggered
at the next system MMR read.
WORKAROUND:
This is usually not an issue because the context will be restored before returning from an interrupt in most cases.
In cases like the one described, it is sufficient to load the RETI register (before the above "raise; rti;" sequence) with a location
where speculative fetches will not cause hardware errors.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
DESCRIPTION:
This anomaly applies to cases where:
1) Memory DMA (MDMA) channels are used in 32-bit mode (WDSIZE in MDMA_yy_CONFIG = 0b10).
AND
2) Traffic Control is enabled to group accesses of the same direction together (DMA_TC_PER register contains non-zero fields).
In this particular case, high and low words may be inverted and/or interrupts may be lost.
WORKAROUND:
This anomaly is avoided if MDMA channels are used in 16-bit mode or if traffic control is disabled (DMA_TC_PER = 0x0000).
Note: on this device, the 16-bit MDMA is more efficient than the 32-bit mode for transfers from L1 to external memory and vice versa.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000281 - False Hardware Error Exception when ISR Context Is Not Restored:
05000282 - Memory DMA Corruption with 32-Bit Data and Traffic Control:
ISR_Exit:
Rx = [Py];
raise 14;
rti;
// instruction C
// instruction A
// instruction B
NR003532D | Page 33 of 45 | July 2008
ADSP-BF531/BF532/BF533