ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet
ADSP-BF532SBST400
Specifications of ADSP-BF532SBST400
Related parts for ADSP-BF532SBST400
ADSP-BF532SBST400 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ADSP-BF531/ADSP-BF532/ADSP-BF533 PERIPHERALS Parallel peripheral interface PPI, supporting ITU-R 656 video data formats ...
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... F: Changed from Rev Rev. F Corrected all document errata Revised text under Revised Electrical Characteristics ............................... 23 Removed the Power Dissipation section. See Estimating Power for the ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229) and see Table 14 Corrected SPI timing master ...................................... Corrected SPI timing slave ........................................ Retitled Environmental Conditions to Thermal Characteristics ...
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... This translates into longer battery life for portable appliances. SYSTEM INTEGRATION The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-a-chip solutions for the next gener- ation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a ...
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... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
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... Booting The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- tain a small boot kernel, which configures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM ...
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... Figure 5. ADSP-BF533 Internal/External Memory Map Event Handling The event controller on the processors handle all asynchronous and synchronous events to the processor. The ADSP-BF531/ ADSP-BF532/ADSP-BF533 processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Pri- oritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event ...
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... When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors’ event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event con- troller works with the system interrupt controller to prioritize and control all system events ...
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... The processor real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the pro- cessor low power state ...
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... SCLK TIMERS There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. Three timers have an external pin that can be configured either as a pulse-width modulator (PWM) or timer output input to ADSP-BF531/ADSP-BF532/ADSP-BF533 clock the timer mechanism for measuring pulse widths and periods of external events. These timers can be synchro- ...
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... The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA cal layer link specification (SIR) protocol. GENERAL-PURPOSE I/O PORT F The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have 16 bidirectional, general-purpose I/O pins on Port F (PF15–0). Each general-purpose I/O pin can be individually controlled by manipulation of the GPIO control, status and interrupt registers: • ...
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... DMA engines that work autonomously from the processor core. DYNAMIC POWER MANAGEMENT The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pro- vides four operating modes, each with a different performance/ power profile. In addition, dynamic power management pro- vides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Active Operating Mode—Moderate Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories. ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 For further details on the on-chip voltage regulator and related board design guidelines, see the Switching Regulator Design 100% Considerations for ADSP-BF533 Blackfin Processors (EE-228) applications note on the Analog Devices web site log.com)—use site search on “EE-228”. CLOCK SIGNALS for regula- ...
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... Signal Name CSEL1– BOOTING MODES “CO ARSE” ADJUSTMENT ON-THE-FLY The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have two mechanisms (listed in internal L1 instruction memory after a reset. A third mode is ÷ CCLK provided to execute from external memory, bypassing the boot sequence. SCLK ÷ Table 8. Booting Modes BMODE1– ...
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... Frequently used instructions are encoded in 16 bits. ADSP-BF531/ADSP-BF532/ADSP-BF533 DEVELOPMENT TOOLS The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are supported by a complete set of CROSSCORE hardware development tools, including Analog Devices emula- tors and VisualDSP++ emulator hardware that supports other Blackfin processors also fully emulates the processor ...
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... Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF531/ADSP-BF532/ADSP-BF533 proces- sors to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allow- ing inspection and modification of memory, registers, and processor stacks ...
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... RELATED DOCUMENTS The following publications that describe the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • Getting Started With Blackfin Processors • ADSP-BF533 Blackfin Processor Hardware Reference • Blackfin Processor Programming Reference • ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 PIN DESCRIPTIONS The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin definitions are listed in Table 9. All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. These pins are all driven high, with the exception of CLKOUT, which toggles at the system clock rate ...
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... SPORT0 Receive Data Primary DR0SEC I SPORT0 Receive Data Secondary TSCLK0 I/O SPORT0 Transmit Serial Clock TFS0 I/O SPORT0 Transmit Frame Sync DT0PRI O SPORT0 Transmit Data Primary DT0SEC O SPORT0 Transmit Data Secondary RSCLK1 I/O SPORT1 Receive Serial Clock ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev Page November 2008 Driver 1 Type ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 9. Pin Descriptions (Continued) Pin Name Type Function RFS1 I/O SPORT1 Receive Frame Sync DR1PRI I SPORT1 Receive Data Primary DR1SEC I SPORT1 Receive Data Secondary TSCLK1 I/O SPORT1 Transmit Serial Clock TFS1 I/O SPORT1 Transmit Frame Sync DT1PRI O SPORT1 Transmit Data Primary ...
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... When V < 2.25 V, on-chip voltage regulation is not supported. DDEXT 4 Applies to all input and bidirectional pins except CLKIN. 5 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum V the input V , because V (maximum) approximately equals V DDEXT OH RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1– ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 The following three tables describe the voltage/frequency requirements for the processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum Table 10. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models Parameter f CCLK Frequency (V =1 ...
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... Applies to three-statable pins. 8 Applies to all signal pins. 9 Guaranteed, but not tested. 10 See the ADSP-BF533 Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes. 11 See Table 16 for the list of I power vectors covered by various Activity Scaling Factors (ASF). ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 System designers should refer to Estimating Power for the ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229), which provides detailed information for optimizing designs for lowest power. All topics discussed in this section are described in detail in EE-229. Total power dissipation has two components: 1. Static, including leakage current 2 ...
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... N/A N/A 600 N/A N/A N/A N/A 1 The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of 2 Valid temperature and voltage ranges are model-specific. See ADSP-BF531/ADSP-BF532/ADSP-BF533 Voltage (V ) DDINT 18.1 19.4 21.0 22.3 24.0 30 ...
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... Guide on Page Rating –0 +1.4 V –0 +3.8 V –0 +3.8 V –0 0.5 V DDEXT 200 pF Table 20. Package Brand Information –65°C to +150°C Brand Key 125°C ADSP-BF53x Either ADSP-BF531, ADSP-BF532, or ADSP-BF533 Table 19 outside speci- DDEXT vvvvvv.x 1 n.n yyww Rev Page November 2008 ...
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... Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator). t CKIN CLKIN t t CKINL RESET ADSP-BF531/ADSP-BF532/ADSP-BF533 system clocks exceeding the maximum limits allowed for the processor, including system clock restrictions related to supply voltage. 5 period is 50 ns. CKIN CKINH t WRST Figure 11 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Asynchronous Memory Read Cycle Timing Table 22. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics t Output Delay After CLKOUT ...
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... CYCLES CLKOUT t DO AMSx ABE1–0 ABE, ADDRESS ADDR19– AWE t SARDY ARDY t ENDAT DATA15–0 WRITE DATA ADSP-BF531/ADSP-BF532/ADSP-BF533 1 1 ACCESS PROGRAMMED WRITE HOLD EXTENDED 1 CYCLE ACCESS 2 CYCLES 1 CYCLE HARDY t SARDY Figure 13. Asynchronous Memory Write Cycle Timing Rev Page November 2008 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 SDRAM Interface Timing 1 Table 24. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before CLKOUT SSDAT t DATA Hold After CLKOUT HSDAT Switching Characteristics t Command, ADDR, Data Delay After CLKOUT DCAD t Command, ADDR, Data Hold After CLKOUT HCAD t Data Disable After CLKOUT ...
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... CLKOUT High to BG Deasserted Hold Time EBG t CLKOUT High to BGH High Setup DBH t CLKOUT High to BGH Deasserted Hold Time EBH CLKOUT AMSx ADDR19-1 ABE1-0 AWE ARE BG BGH ADSP-BF531/ADSP-BF532/ADSP-BF533 V = 1.8 V DDEXT LQFP/PBGA Packages Min Max 4.6 1.0 4.5 4.5 6.0 6.0 6.0 6 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Parallel Peripheral Interface Timing Table 26 and Figure 16 through Figure 21 on Page 35 parallel peripheral interface operations. Table 26. Parallel Peripheral Interface Timing Parameter Timing Requirements t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK t External Frame Sync Setup Before PPI_CLK Edge SFSPE (Nonsampling Edge for Rx, Sampling Edge for Tx) ...
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... PPI_CLK POLC = 0 PPI_CLK POLC = 1 t SFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA Figure 18. PPI GP Rx Mode with External Frame Sync Timing (Bit 8 of PPI_CONTROL Set) ADSP-BF531/ADSP-BF532/ADSP-BF533 FRAME SYNC IS SAMPLED FOR DATA1 IS DATA0 SAMPLED t HFSPE t SFSPE t HDRPE Figure 17. PPI GP Rx Mode with External Frame Sync Timing ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 FRAME SYNC IS DRIVEN OUT PPI_CLK POLC = 0 PPI_CLK POLC = 1 t DFSPE t HOFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA PPI_CLK POLC = 0 PPI_CLK POLC = 1 POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Figure 19. PPI GP Tx Mode with Internal Frame Sync Timing ...
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... EDGE PPI_CLK POLC = 0 PPI_CLK POLC = 1 t SFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA Figure 21. PPI GP Tx Mode with External Frame Sync Timing (Bit 8 of PPI_CONTROL Set) ADSP-BF531/ADSP-BF532/ADSP-BF533 DATA DRIVING/ FRAME SYNC SAMPLING EDGE t HFSPE t DDTPE t HDTPE Rev Page November 2008 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Serial Ports Table 27 through Table 30 on Page 37 and through Figure 23 on Page 38 describe Serial Port operations. Table 27. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx HFSE t Receive Data Setup Before RSCLKx SDRE ...
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... DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLKx t DFSI t t HOFSI SFSI TFSx t DDTI t HDTI DTx NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE. ADSP-BF531/ADSP-BF532/ADSP-BF533 1.8 V DDEXT LQFP/PBGA Packages Min Max 10 and t . DTENLFS DDTLFSE /2, then t and t apply ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 EXTERNAL RFSx IN MULTICHANNEL MODE WITH MFD = 0 RSCLKx RFSx DTx LATE EXTERNAL TFSx TSCLKx TFSx DTx DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTTE/I t DTENLFS t DTENE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTTE/I t DTENLFS t DTENE/I 1ST BIT t DDTLFSE Figure 23. External Late Frame Sync Rev ...
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... SPIxSELy (OUTPUT SDSCIM SCKx (CPOL = 0) (OUTPUT) t SCKx (CPOL = 1) (OUTPUT) MOSIx (OUTPUT) CPHA=1 MISOx (INPUT) MOSIx MSB (OUTPUT) CPHA=0 t SSPIDM MSB MISOx VALID (INPUT) ADSP-BF531/ADSP-BF532/ADSP-BF533 V = 1.8 V DDEXT LQFP/PBGA Packages Min Max –1.5 2t SCLK 2t –1.5 SCLK 2t –1.5 SCLK 4t SCLK 2t SCLK 2t SCLK 6 –1 SPICHM ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Serial Peripheral Interface (SPI) Port—Slave Timing Table 32. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period SPICLK t Last SCK Edge to SPISS Not Asserted HDS t Sequential Transfer Delay ...
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... CLKOUT (SAMPLE CLOCK) Rx RECEIVE INTERNAL UART RECEIVE INTERRUPT Tx TRANSMIT INTERNAL UART TRANSMIT INTERRUPT ADSP-BF531/ADSP-BF532/ADSP-BF533 Figure 26, DATA[8:5] START DATA[8:5] Figure 26. UART Port—Receive and Transmit Timing Rev Page November 2008 STOP UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ STOP[2:1] UART TRANSMIT BIT SET BY PROGRAM; ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 General-Purpose I/O Port F Pin Cycle Timing Table 33. General-Purpose I/O Port F Pin Cycle Timing Parameter Timing Requirement t GPIO Input Pulse Width WFI Switching Characteristic t GPIO Output Delay from CLKOUT Low DFO CLKOUT PFx (OUTPUT) PFx (INPUT) Min t SCLK t DFO GPIO OUTPUT ...
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... The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode. 2 The minimum time for t is one cycle, and the maximum time for t HTO CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) ADSP-BF531/ADSP-BF532/ADSP-BF533 V DDEXT Min equals (2 –1) cycles. HTO ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 JTAG Test and Emulation Port Timing Table 35. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High SSYS t System Inputs Hold After TCK High ...
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... SOURCE VOLTAGE (V) Figure 31. Drive Current A (V DDEXT 150 100 50 0 –50 –100 –150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 32. Drive Current A (V DDEXT ADSP-BF531/ADSP-BF532/ADSP-BF533 150 100 2.75V DDEXT V = 2.50V DDEXT – 2.25V DDEXT –100 –150 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 –20 –40 –60 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 36. Drive Current C (V DDEXT –10 –20 –30 –40 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 37. Drive Current C (V DDEXT 100 –20 –40 –60 –80 –100 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 38. Drive Current C (V ...
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... C DECAY V equal to 0.1 V for V (nominal 0.5 V for DDEXT V (nominal) = 2.5 V/3.3 V. DDEXT ADSP-BF531/ADSP-BF532/ADSP-BF533 The time t signal switches, to when the output voltage decays V from the measured output high or output low voltage. Figure 42 is 0.95 V for MEAS (nominal) = 2.5 V/ ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 16 14 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 45. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 1.75 V DDEXT 14 12 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 46. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver ...
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... Figure 52. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 2.25 V DDEXT RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 53. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 3.65 V DDEXT ADSP-BF531/ADSP-BF532/ADSP-BF533 200 250 Figure 54. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for FALL TIME ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board, use CASE JT where Junction temperature ( C Case temperature ( C) measured by customer at top CASE center of package. = From Table 36 through Table 38 Power dissipation (see the power dissipation discussion D and the tables on on Page 24 ...
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... BMODE0 N4 GND BMODE1 P3 GND BR D14 GND CLKIN A12 GND CLKOUT B14 GND DATA0 M9 GND DATA1 N9 GND DATA2 P9 GND DATA3 M8 GND ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 40 Ball No. Signal Ball No. N8 GND L6 P8 GND L8 M7 GND L10 N7 GND M4 P7 GND M10 M6 GND P14 N6 MISO E2 P6 MOSI ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 40. 160-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No C13 DDEXT A2 PF8 C14 A3 PF9 D1 A4 PF10 D2 A5 PF11 D3 A6 PF14 D4 A7 PPI2 D5 A8 RTXO D6 A9 RTXI D7 A10 GND D8 A11 XTAL D9 A12 CLKIN D10 A13 VROUT0 D11 A14 GND ...
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... Figure 57 lists the top view of the CSP_BGA ball configuration. Figure 58 lists the bottom view of the CSP_BGA ball configuration. ADSP-BF531/ADSP-BF532/ADSP-BF533 KEY GND DDINT DDRTC V V I/O DDEXT ROUT Figure 57. 160-Ball CSP_BGA Ground Configuration (Top View KEY GND DDINT DDRTC V V I/O DDEXT ROUT Figure 58 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 169-BALL PBGA BALL ASSIGNMENT Table 41 lists the PBGA ball assignment by signal. Page 55 lists the PBGA ball assignment by ball number. Table 41. 169-Ball PBGA Ball Assignment (Alphabetically by Signal) Signal Ball No. Signal ABE0 H16 DATA4 ABE1 H17 DATA5 ADDR1 J16 DATA6 ADDR2 J17 ...
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... B15 SA10 H7 B16 GND H8 B17 SWE H9 C1 PF1 H10 C2 PF3 H11 C16 ARDY H12 C17 BR H16 D1 SCK H17 D2 PF0 J1 ADSP-BF531/ADSP-BF532/ADSP-BF533 Signal Ball No. Signal CLKOUT J2 RSCLK1 AMS0 J6 V DDEXT MOSI J7 GND MISO J8 GND AMS1 J9 GND AMS2 J10 GND DT1PRI J11 GND DT1SEC ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 A1 BALL PAD CORNER TOP VIEW Figure 59. 169-Ball PBGA Ground Configuration (Top View BOTTOM VIEW Figure 60. 169-Ball PBGA Ground Configuration (Bottom View) Rev Page November 2008 KEY GND DDINT I/O DDEXT BALL PAD CORNER KEY: V GND DDINT V I/O DDEXT ROUT NC V ROUT ...
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... BMODE0 96 GND BMODE1 95 GND BR 163 GND CLKIN 10 GND CLKOUT 169 GND DATA0 116 GND DATA1 115 GND DATA2 114 GND ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 44 on Page 58 Lead No. Signal Lead No. 113 GND 88 112 GND 89 110 GND 90 109 GND 91 108 GND 92 105 GND 97 104 GND ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 44. 176-Lead LQFP Pin Assignment (Numerically by Lead Number) Lead No. Signal Lead No. 1 GND 41 2 GND 42 3 GND 43 4 VROUT1 44 5 VROUT0 DDEXT 7 GND 47 8 GND 48 9 GND 49 10 CLKIN 50 11 XTAL DDEXT 13 RESET 53 14 NMI 54 15 GND 55 16 RTXO 56 17 ...
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... OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ADSP-BF531/ADSP-BF532/ADSP-BF533 0.75 1.60 0.60 MAX 0.45 176 1 PIN 1 0.20 0.09 7° 3.5° 0° 44 0.08 MAX 45 COPLANARITY VIEW A LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BGA Figure 61 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 A1 BALL CORNER 1.70 1.60 1.35 2.50 2.23 1.97 12.10 12.00 SQ 11. 10.40 BSC SQ 0.80 BSC TOP VIEW DETAIL A DETAIL A SEATING PLANE BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-205-AE WITH THE EXCEPTION TO BALL DIAMETER. Figure 62. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] ...
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... Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2 Plastic Ball Grid Array (PBGA) B-169 AUTOMOTIVE PRODUCTS Some ADSP-BF531/ADSP-BF532/ADSP-BF533 models are available for automotive applications with controlled manufac- turing. Note that these special models may have specifications that differ from the general release models. ...
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... ADSP-BF532SBBZ400 –40°C to +85°C 400 MHz ADSP-BF532SBBC400 –40°C to +85°C 400 MHz 2 ADSP-BF532SBBCZ400 –40°C to +85°C 400 MHz ADSP-BF532SBST400 –40°C to +85°C 400 MHz 2 ADSP-BF532SBSTZ400 –40°C to +85°C 400 MHz 2 ADSP-BF533SBBZ400 –40°C to +85°C 400 MHz ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev Page November 2008 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03728-0-11/08(F) Rev Page November 2008 ...